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freescale semiconductor advance information document number: mm912_634d1 rev. 4.0, 5/2011 ? freescale semiconductor, inc., 2010-2011. all rights reserved. this document contains certain in formation on a new product. specific ations and information herein are subject to change without notice. integrated s12 based relay driver with lin the mm912g634 (48 kb) and mm912h634 (64 kb) are integrated single package soluti ons that integrates an hcs12 microcontroller with a smartmos analog control ic. the die to die interface (d2d) controlled analog die combines system base chip and application specific functions, including a lin transceiver. features ? 16-bit s12 cpu, 64/48 kbyte p-flash, ? 6.0 kbyte ram; 4/2 kbyte d-flash ? background debug (bdm) & debug module (dbg) ? die to die bus interface for transparent memory mapping ? on-chip oscillator & two independent watchdogs ? lin 2.1 physical layer interface with integrated sci ? 10 digital mcu gpios shared with spi (pa7?0, pe1?0) ? 10-bit, 15 channel - analog to digital converter (adc) ? 16-bit, 4 channel - timer module (tim16b4c) ? 8-bit, 2 channel - pulse width modulation module (pwm) ? six high voltage / wake-up inputs (l5?0) ? three low voltage gpios (pb2?0) ? low power modes with cyclic sense & forced wake-up ? current sense module with selectable gain ? reverse battery protected voltage sense module ? two protected low side outputs to drive inductive loads ? two protected high side outputs ? chip temperature sensor ? hall sensor supply & integrated voltage regulator(s) figure 1. simplified application diagram ordering information see page 2. mm912_634 48-pin lqfp, 7.0 mm x 7.0 mm ae suffix: exposed pad option ap suffix: non exposed pad option mm912_634 vsense vs1 vs2 lin vdd agnd r eset r e s e t_a pa0/miso ls1 ls2 isenseh* hs1 hs2* test_a lgnd battery sense l1 m tclk l2 l3 l4* isensel* pgnd l0 l5* hall sensor hsup hall sensor ptb0/ad0/rx/tim0ch0 ptb1/ad1/tx/tim0ch1 ptb2/ad2/pwm/tim0ch2 pa1/mosi pa2/sck pa3/ss pa4 pa5 pa6 pa7 bkgd/modc pe0/extal pe1/xtal test adc25 vddd2d vddx vddrx dgnd vssrx vssd2d power supply lin interface adc supply 2.5 v suppy 5.0 v supply digital ground reset 5.0 v digital i/o debug and external oscillator mcu test * feature not availablre in all analog options low side drivers current sense moe hall sensor supply 5.0 v gpi/o with optional pull-up (shared with adc, pwm, timer, and sci) 12 v light/led and switch supply analog/digita inputs (high voltage and wake-up capable) analog test
ordering information mm912_634 advance information, rev. 4.0 freescale semiconductor 2 1 ordering information table 1. ordering information device (add an r2 suffix for tape and reel orders) temperature range (t a ) package max. bus frequency in mhz (f busmax ) flash (kb) data flash (kb) ram (kb) analog option (1) mm912g634cm1ae -40c to 125c lqfp48-ep 20 48 (2) 2 (3) 2 (4) a1 MM912G634CV1AE -40c to 105c lqfp48-ep 20 48 (2) 2 (3) 2 (4) a1 mm912g634cv2ap -40c to 105c lqfp48 16 48 (2) 2 (3) 2 (4) a2 mm912h634cm1ae -40c to 125c lqfp48-ep 20 64 4 6 a1 mm912h634cv1ae -40c to 105c lqfp48-ep 20 64 4 6 a1 note: 1. see table 2 . 2. the 48 kb flash option (mm912 g 634) using the same s12i64 mcu with the tested flashsize reduced to 48 kb. this will limit the usable flash area to the first 48 kb (0x3_4000-0x3_ffff). 3. the 48 kb flash option (mm912 g 634) using the same s12i64 mcu with the tested data - flashsize reduced to 2.0 kb. this will limit the usable data flash area to t he first 2.0 kb (0x0_4400-0x0_4bff). 4. the 48 kb flash option (mm912 g 634) using the same s12i64 mcu with the tested ra msize reduced to 2.0 kb. this will limit the usable ram area to the first 2.0 kb (0x0_2800-0x0_2fff). table 2. analog options (5) feature a1 a2 battery sense module yes yes current sense module yes no 2nd high side output (hs2) yes yes wake-up inputs (lx) l0?l5 l0?l3 hall supply output (hsup) yes yes lin module yes yes note: 5. this table only highlights the analog die differences between t he derivatives. features highlighted as ?no? or the lx inputs not mentioned are not available in the specific option and not bonded out and/or not tested. see section 4.3.3, ?analog die options for detailed information.
ordering information mm912_634 advance information, rev. 4.0 freescale semiconductor 3 the device part number is following the standard scheme in table 3 : table 3. part numbering scheme mm 9 cc f xxx r t v ppp rr product category memory type core memory size a analog core/target revision temperature range variation package designator tape and reel indicator mm- qualified standard 9 = flash, otp 08 = hc08 1 k (default a) i = 0 c to 85 c (default blank) sm- custom device blank = rom 12 = hc12 b 2 k c = -40 c to 85 c pm- prototype device c 4 k v = -40 c to 105 c d 8 k m = -40 c to 125 c e 16 k f 32 k g 48 k h 64 k i 96 k j 128 k
mm912_634 advance information, rev. 4.0 freescale semiconductor 4 table of contents 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 mm912_634 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2 mcu die signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.3 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.4 supply currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.5 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.6 dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.7 thermal protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.8 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.9 additional test information iso7637-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4 functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.2 device register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.3 mm912_634 - analog die overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.6 die to die interface - target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.8 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 4.9 wake-up / cyclic sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.10 window watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.11 hall sensor supply output - hsup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.12 high side drivers - hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4.13 low side drivers - lsx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 4.14 pwm control module (pwm8b2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.15 lin physical layer interface - lin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 4.16 serial communication interface (s08sciv4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.17 high voltage inputs - lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.18 general purpose i/o - ptb[0?2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.19 basic timer module - tim (tim16b4c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 4.20 analog digital converter - adc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 4.21 current sense module - isense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 4.22 temperature sensor - tsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 4.23 supply voltage sense - vsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 4.24 internal supply voltage sense - vs1sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 4.25 internal bandgap reference voltage sense - bandgap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 4.26 mm912_634 - analog die trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 4.27 mm912_634 - mcu die overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 4.28 port integration module (s12ipimv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 4.29 memory map control (s12pmmcv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 4.30 interrupt module (s12sintv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 4.31 background debug module (s12sbdmv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 4.32 s12s debug module (s12sdbgv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 4.33 security (s12x9secv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 4.34 impact on mcu modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 4.35 secure firmware code overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 4.36 initialization of a virgin device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 4.37 impact of security on test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 4.38 s12 clock, reset and power management unit (s12cpmu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 4.39 serial peripheral interface (s12spiv5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 4.40 64 kbyte flash module (s12ftmrc64k1v1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 4.41 die-to-die initiator (d2div1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
mm912_634 advance information, rev. 4.0 freescale semiconductor 5 5 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 5.1 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
mm912_634 advance information, rev. 4.0 freescale semiconductor 6 figure 2. device block diagram cascaded voltage regulators vdd = 2.5v vddx = 5v die to die interface reset control module window watchdog module reset_a vs2 agnd 18v clamped output module hs1 ls2 hsup vsense isensel lx input module lin vs1 d2ddat1 d2ddat0 d2dclk d2dint wake up module current sense module interrupt control module low side control module vbat sense module analog multiplexer l3 l2 l1 l0 hs2 ls1 isenseh pgnd chip temp sense module high side control module vddx vdd sci d2ddat3 d2ddat2 osc (trimmable) adc 10bit ptb1/ad1/tx/timch1 gpio ptb0/ad0/rx/timch0 ptb2/ad2/pwm/timch 2 lin physical layer internal bus analog die internal bus cpu 12-v1 cpu register alu d2di flash 64k bytes with ecc data flash 4k bytes with ecc ram 6k byte debug module include 64 byte trace buffer ram reset generation and test entry amplitude contr. low power pierce osc pll with freq. modulation option osc clock monitor single-wire background debug module cop watchdog periodic interrupt interrupt module spi ddra mosi miso sck porta mcu die ss pa0 pa1 pa2 pa3 pa4 pa5 test pe1/xtal pe0/extal bkgd/modc reset vssrx vddrx vssd2d vddd2d dgnd l5 l4 4 channel timer module adc2p5 lgnd test interface tclk test_a 2 channel pwm module vreg 1.8v core 2.7v flash pa7 porte[0:1] pa6
pin assignment mm912_634 advance information, rev. 4.0 freescale semiconductor 7 2 pin assignment figure 3. mm912_634 pin out note the device exposed pad (package option ae only) is recommended to be connected to gnd. not all pins are available for analog die option 2. see section 4.3.3, ?analog die options for details. 1 2 3 4 5 6 7 8 9 10 11 12 pa6 vssrx vddrx pe0/extal pe1/xtal test pa5 pa4 pa3 pa2 pa1 pa0 36 35 34 33 32 31 30 29 28 27 26 25 l5 ptb0 lgnd l4 l3 l2 l1 l0 agnd adc2p5 ptb2 ptb1 37 38 39 40 41 42 43 44 45 46 47 48 ls1 bkgd pa7 pgnd ls2 isensel isenseh nc test_a tclk reset_a reset 24 23 22 21 20 19 18 17 16 15 14 13 lin vddd2d vssd2d hsup hs2 hs1 vs2 vs1 vsense dgnd vddx vdd
pin assignment mm912_634 advance information, rev. 4.0 freescale semiconductor 8 2.1 mm912_634 pin description the following table gives a brief description of all available pi ns on the mm912_634 package. refer to the highlighted chapter for detailed information. table 4. mm912_634 pin description pin # pin name formal name description 1pa6 mcu pa6 general purpose port a input or output pin 6. see section 4.28, ?port integration module (s12ipimv1) 2 pe0/extal mcu oscillator extal is one of the optional crystal/resonat or driver and external clock pins. on reset, all the device clocks are derived from the internal reference clock and port pe may be used for general purpose i/o. see section 4.38.2.2, ?extal and xtal and section 4.28, ?port integration module (s12ipimv1) . 3 pe1/xtal mcu oscillator xtal is one of the optional crystal/resonat or driver and external clock pins. on reset, all the device clocks are derived from the internal reference clock and port pe may be used for general purpose i/o. see section 4.38.2.2, ?extal and xtal and section 4.28, ?port integration module (s12ipimv1) . 4test mcu test this input only pin is reserved for test. th is pin has a pull-down device. the test pin must be tied to evss in user mode. 5pa5 mcu pa5 general purpose port a input or output pin 5. see section 4.28, ?port integration module (s12ipimv1) 6pa4 mcu pa4 general purpose port a input or output pin 4. see section 4.28, ?port integration module (s12ipimv1) . 7 pa3 mcu pa3 / ss general purpose port a input or output pin 3, shared with the ss signal of the integrated spi interface. see section 4.28, ?port integration module (s12ipimv1) . 8 pa2 mcu pa2 / sck general purpose port a input or output pin 2, shared with the sclk signal of the integrated spi interface. see section 4.28, ?port integration module (s12ipimv1) . 9 pa1 mcu pa1 / mosi general purpose port a input or output pin 1, shared with the mosi signal of the integrated spi interface. see section 4.28, ?port integration module (s12ipimv1) . 10 pa0 mcu pa0 / miso general-purpose port a input or output pin 0, shared with the miso signal of the integrated spi interface. see section 4.28, ?port integration module (s12ipimv1) . 11 vssrx mcu 5.0 v ground ground for the mcu 5.0 v power supply. 12 vddrx mcu 5.0 v supply mcu 5.0 v - core- and flash voltage regulator supply. see section 4.27, ?mm912_634 - mcu die overview . 13 vssd2d mcu 2.5 v ground ground for the mcu 2.5 v power supply. 14 vddd2d mcu 2.5 v supply mcu 2.5 v - mcu die-to-die interface power supply. see section 4.27, ?mm912_634 - mcu die overview . 15 vdd voltage regulator output 2.5 v +2.5 v main voltage regulator output pin. external capacitor (cvdd) needed. see section 4.5, ?power supply . 16 vddx voltage regulator output 5.0 v +5.0 v main voltage regulator output pin. external capacitor (cvddx) needed. see section 4.5, ?power supply . 17 dgnd digital ground this pin is the device digi tal ground connection for the 5.0 v and 2.5v logic. dgnd, lgnd, and agnd are internally conne cted to pgnd via a back to back diode. 18 vsense voltage sense battery voltage sense input. this pin can be connected directly to the battery line for voltage measurements. the voltage present at this input is scaled down by an internal voltage divider, and can be rout ed to the internal adc via the analog multiplexer.the pin is self-protected against reverse battery connections. an external resistor (rvsenxse) is needed for protection (6) . see section 4.23, ?supply voltage sense - vsense . note: this pin function is not available on all device configurations. note: 6. an optional filter capacitor cvsense is recommended to be placed between the board connector and dvsense to gnd for increased esd performance.
pin assignment mm912_634 advance information, rev. 4.0 freescale semiconductor 9 19 vs1 power supply pin 1 this pin is the device power supply pin 1. vs1 is primarily supplying the vddx voltage regulator and the hall sensor supply regulator (hsup). vs1 can be sensed via a voltage divider through the ad converter. reverse battery protection diode is required. see section 4.5, ?power supply 20 vs2 power supply pin 2 this pin is the device power supply pin 2. vs2 supplies th e high side drivers (hsx). reverse battery protection diode required. see section 4.5, ?power supply 21 hs1 high side output 1 this pin is the first high side output. it is supplied through the vs2 pin. it is designed to drive small resistive loads with optional pwm. in cyclic sense mode, this output will activate periodically during low power mode. see section 4.12, ?high side drivers - hs . 22 hs2 high side output 2 this pin is the second high side output. it is supplied through the vs2 pin. it is designed to drive small resist ive loads with optional pwm. in cyclic sense mode, this output will activate periodically during low power mode. see section 4.12, ?high side drivers - hs . note: this pin function is not available on all device configurations. 23 hsup hall sensor supply output this pin is designed as an 18 v regulator to drive hall sensor elements. it is supplied through the vs1 pin. an external capacitor (chsup) is needed. see section 4.11, ?hall sensor supply output - hsup . note: this pin function is not available on all devi ce configurations. 24 lin lin bus i/o this pin represents the single-wire bus transmitter and receiver. see section 4.15, ?lin physical layer interface - lin . note: this pin function is not available on all device configurations. 25 lgnd lin ground pin this pin is the device lin ground c onnection. dgnd, lgnd, and agnd are internally connected to pgnd via a back to back diode. 26 ptb0 general purpose i/o 0 this is the general purpose i/o pin 0 based on vddx with the following shared functions: ? ptb0 - bidirectional 5.0 v (vddx) digita l port i/o with selectable internal pull-up resistor. ? ad0 - analog input channel 0, 0?2.5v (adc2p5) analog input ? tim0ch0 - timer channel 0 input/output ? rx - selectable connection to lin / sci see section 4.18, ?general purpose i/o - ptb[0?2] . 27 ptb1 general purpose i/o 1 this is the general purpose i/o pin 1 based on vddx with the following shared functions: ? ptb1 - bidirectional 5.0 v (vddx) digita l port i/o with selectable internal pull-up resistor. ? ad1 - analog input channel 1, 0?2.5 v (adc2p5) analog input ? tim0ch1 - timer channel 1 input/output ? tx - selectable connection to lin / sci see section 4.18, ?general purpose i/o - ptb[0?2] . 28 ptb2 general purpose i/o 2 this is the general purpose i/o pin 2 based on vddx with the following shared functions: ? ptb2 - bidirectional 5.0 v (vddx) digita l port i/o with selectable internal pull-up resistor. ? ad2 - analog input channel 2, 0?2.5v (adc2p5) analog input ? tim0ch2 - timer channel 2 input/output ? pwm - selectable connection to pwm channel 0 or 1 see section 4.18, ?general purpose i/o - ptb[0?2] . 29 adc2p5 adc reference voltage this pin represents the adc reference vo ltage and has to be connected to a filter capacitor. see section 4.20, ?analog digital converter - adc 30 agnd analog ground pin this pin is the device a nalog to digital converter ground connection. dgnd, lgnd and agnd are internally connected to pgnd via a back to back diode. table 4. mm912_634 pin description pin # pin name formal name description
pin assignment mm912_634 advance information, rev. 4.0 freescale semiconductor 10 31 l0 high voltage input 0 this pins is the high voltage input 0 with the following shared functions: ? l0 - digital high voltage input 0. when used as digital input, a series resistor (rlx) must be used to protect against automotive transients. (7) ? ad3 - analog input 3 with selectable divider for 0?5.0 v and 0?18 v measurement range. ? wu0 - selectable wake-up input 0 fo r wake up and cyclic sense during low power mode. see section 4.17, ?high voltage inputs - lx 32 l1 high voltage input 1 this pins is the high voltage input 1 with the following shared functions: ? l1 - digital high voltage input 1. when used as digital input, a series resistor (rlx) must be used to protect against automotive transients. (7) ? ad4 - analog input 4 with selectable divider for 0?5.0 v and 0?18 v measurement range. ? wu1 - selectable wake-up input 1 for wake-up and cyclic sense during low power mode. see section 4.17, ?high voltage inputs - lx 33 l2 high voltage input 2 this pins is the high voltage input 2 with the following shared functions: ? l2 - digital high voltage input 2. when used as digital input, a series resistor (rlx) must be used to protect against automotive transients. (7) ? ad5 - analog input 5 with selectable divider for 0?5.0 v and 0?18 v measurement range. ? wu2 - selectable wake-up input 2 for wake-up and cyclic sense during low power mode. see section 4.17, ?high voltage inputs - lx . note: this pin functi on is not available on all device configurations. 34 l3 high voltage input 3 this pins is the high voltage input 3 with the following shared functions: ? l3 - digital high voltage input 3. when used as digital input, a series resistor (rlx) must be used to protect against automotive transients. (7) ? ad6 - analog input 6 with selectable divider for 0?5.0 v and 0?18 v measurement range. ? wu3 - selectable wake-up input 3 for wake-up and cyclic sense during low power mode. see section 4.17, ?high voltage inputs - lx . note: this pin functi on is not available on all device configurations. 35 l4 high voltage input 4 this pins is the high voltage input 4 with the following shared functions: ? l4 - digital high voltage input 4. when used as digital input, a series resistor (rlx) must be used to protect against automotive transients. (7) ? ad7 - analog input 7 with selectable divider for 0?5.0 v and 0?18 v measurement range. ? wu4 - selectable wake-up input 4 for wake-up and cyclic sense during low power mode. see section 4.17, ?high voltage inputs - lx . note: this pin functi on is not available on all device configurations. 36 l5 high voltage input 5 this pins is the high voltage input 5 with the following shared functions: ? l5 - digital high voltage input 5. when used as digital input, a series resistor (rlx) must be used to protect against automotive transients. (7) ? ad8 - analog input 8 with selectable divider for 0?5.0 v and 0?18 v measurement range. ? wu5 - selectable wake-up input 5 for wake-up and cyclic sense during low power mode. see section 4.17, ?high voltage inputs - lx . note: this pin functi on is not available on all device configurations. note: 7. an optional filter capacitor clx is recommended to be plac ed between the board connector and rlx to gnd for increased esd performance. table 4. mm912_634 pin description pin # pin name formal name description
pin assignment mm912_634 advance information, rev. 4.0 freescale semiconductor 11 2.2 mcu die signal properties this section describes the external mcu signal s. it includes a table of signal properties. 37 ls1 low side output 1 low side output 1 used to drive small inductive loads like relays. the output is short-circuit protected, incl udes active clamp circuitry and can be also controlled by the pwm module. see section 4.13, ?low side drivers - lsx 38 pgnd power ground pin this pin is the device low side ground connection. dgnd, lgnd and agnd are internally connected to pgnd via a back to back diode. 39 ls2 low side output 2 low side output 2 used to drive small inductive loads like relays. the output is short-circuit protected, incl udes active clamp circuitry and can be also controlled by the pwm module. see section 4.13, ?low side drivers - lsx 40 isensel current sense pin l current sense differential input ?low?. th is pin is used in combination with isenseh to measure the voltage drop across a shunt resistor. see section 4.21, ?current sense module - isense . note: this pin function is not available on all device configurations. 41 isenseh current sense pin h current sense differential input ?high?. this pin is used in combination with isensel to measure the voltage drop across a shunt resistor. section 4.21, ?current sense module - isense . note: this pin function is not available on all device configurations. 42 nc not connected this pin is reserved for alter native function and should be left floating. 43 test_a test mode analog die test mode pin for test mode only. this pin must be grounded in user mode! 44 tclk test clock input test mode clock input pin for test mode only. the pin can be used to disable the internal watchdog for development purpose in user mode. see section 4.10, ?window watchdog . the pin is recommended to be grounded in user mode. 45 reset_a reset i/o bidirectional reset i/o pin of the analog di e. active low signal. internal pull-up. v ddx based. see section 4.8, ?resets . to be externally connected to the reset pin. 46 reset mcu reset the reset pin is an active low bidirecti onal control signal. it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. the reset pin has an internal pull-up device to evddx. 47 bkgd mcu background debug and mode the bkgd/modc pin is used as a pseudo-open-drain pin for the background debug communication. it is used as mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset . the bkgd pin has a pull-up device. 48 pa7 mcu pa7 general purpose port a input or output pin 7. see section 4.28, ?port integration module (s12ipimv1) table 5. signal properties summary pin name function 1 pin name function 2 power supply internal pull resistor description ctrl reset state pe0 extal vd drx pupee/ oscpins_en down port e i/o, oscillator pin pe1 xtal v ddrx pupbe/ oscpins_en down port e i/o, oscillator pin reset ? vddrx pullup external reset test ? n.a. reset pin down test input bkgd modc vddrx bkpue up background debug pa7 ? vddrx na na port a i/o table 4. mm912_634 pin description pin # pin name formal name description
pin assignment mm912_634 advance information, rev. 4.0 freescale semiconductor 12 pa6 ? vddrx na na port a i/o pa5 ? vddrx na na port a i/o pa4 ? vddrx na na port a i/o pa3 ss vddrx na na port a i/o, spi pa2 sck vddrx na na port a i/o, spi pa1 mosi vddrx na na port a i/o, spi pa0 miso vddrx na na port a i/o, spi pc1 d2dint vddd2d pupce/ d2den disabled port c i/o, d2di pc0 d2dclk vddd2d na na port c i/o, d2di pd7-0 d2ddat7-0 vddd2d pupde/ d2den disabled port d i/o, d2di table 5. signal properties summary pin name function 1 pin name function 2 power supply internal pull resistor description ctrl reset state
general mm912_634 advance information, rev. 4.0 freescale semiconductor 13 3 electrical characteristics 3.1 general this section contains electrical information for the embedded mc9s12i64 microcontroller die, as well as the mm912_634 analog die. 3.2 absolute maximum ratings absolute maximum ratings are stress ratings only. a function al operation under or outside t hose maxima is not guaranteed. stress beyond those limits may affect the reliabi lity or cause permanent damage of the device. this device contains circuitry protecting against damage due to hi gh static voltage or electrical fields. however, it is advise d that normal precautions be taken to avoid application of any voltage s higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. all voltages are with respect to ground, unless otherwise noted. table 6. absolute maximum elect rical ratings - analog die ratings symbol value unit supply voltage at vs1 and vs2 normal operation (dc) transient conditions (load dump) transient input voltage with external component (according to lin conformance test specification / iso7637-2) v sup(ss) v sup(pk) v sup(tr) -0.3 to 27 -0.3 to 40 (8) v l0?l5 - pin voltage normal operation with a series r lx resistor (dc) transient input voltage with external component (according to lin conformance test specification / iso7637-2) v lxdc v lxtr 27 to 40 (8) v lin pin voltage normal operation (dc) transient input voltage with external component (according to lin conformance test specification / iso7637-2) v busdc v bustr -33 to 40 (8) v supply voltage at vddx v ddx -0.3 to 5.5 v supply voltage at vdd v dd -0.3 to 2.75 v vdd output current i vdd internally limited a vddx output current i vddx internally limited a tclk pin voltage v tclk -0.3 to 10 v reset_a pin voltage v in -0.3 to v ddx +0.3 v input / output pins ptb[0:2] voltage v in -0.3 to v ddx +0.3 v hs1 and hs2 pin voltage (dc) v hs -0.3 to vs2+0.3 v ls1 and ls2 pin voltage (dc) v ls -0.3 to 45 v isenseh and isensel pin voltage (dc) v isense -0.3 to 40 v hsup pin voltage (dc) v hsup -0.3 to vs1+0.3 v vsense pin voltage (dc) v vsense -27 to 40 v note: 8. see section 3.9, ?additional test information iso7637-2
operating conditions mm912_634 advance information, rev. 4.0 freescale semiconductor 14 3.3 operating conditions this section describes the operating condit ions of the device. unless otherwise not ed those conditions apply to all the followi ng data. table 7. maximum electri cal ratings - mcu die (9) ratings symbol value unit 5.0 v supply voltage (supplying the mcu internal regulator for core and flash) v ddrx -0.3 to 6.0 v 2.5 v d2d - supply voltage v ddd2d -0.3 to 3.6 v digital i/o input voltage (pa0...pa7, pe0, pe1) v in -0.3 to 6.0 v extal, xtal (pe0 and pe1 in alternative configuration) v ilv -0.3 to 2.16 v test input v test -0.3 to 10.0 v instantaneous maximum current single pin limit for all digital i/o pins i d -25 to 25 ma instantaneous maximum current single pin limit for extal, xtal i dl -25 to 25 ma note: 9. all digital i/o pins are internally clamped to vssrx and vddrx. table 8. maximum thermal ratings ratings symbol value unit storage temperature t stg -55 to 150 ? c package (lqfp48), thermal resistance r ? ja max. 48 k ? peak package reflow temperature during reflow (10) , (11) t pprt note 11 c notes 10. pin soldering temperature limit is for 10 seconds maximum duration. not designed fo r immersion soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 11. freescale?s package reflow capability meets pb-free requi rements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freesca le.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i .e. mc33xxxd enter 33xxx), and review parametrics. table 9. operating conditions ratings symbol value unit analog die nominal operating voltage v sup 5.5 to 18 v analog die functional operating volt age - device is fully functional. all features are operating. v supop 5.5 to 27 v mcu i/o and supply voltage (12) v ddrx 4.75 to 5.25 v mcu digital logic supply voltage (12) v ddd2d 2.25 to 2.75 v mcu oscillator mm912x634xxxae mm912x634xxxap f osc 4.0 to 16 4.0 to 16 mhz mcu bus frequency mm912x634xxxae mm912x634xxxap f bus f busmax (13) mhz note: 12. during power up and power down sequence always v ddd2d < v ddrx 13. f busmax frequency ratings differ by device and is specified in table 1
supply currents mm912_634 advance information, rev. 4.0 freescale semiconductor 15 3.4 supply currents this section describes the current consum ption characteristics of the device as well as the conditions for the measurements. 3.4.1 measurement conditions all measurements are without output loads . currents are measured in mcu special single chip mode and the cpu code is executed from ram, unless otherwise noted. 3.5 static electrical characteristics all characteristics noted under the following conditions: ?5.5v ? v sup ? 18 v ?-40c ? t a ? 125 c (mm912x634xmxxx) ?-40c ? t a ? 105 c (mm912x634xvxxx) typical values noted reflect the approximate parameter mean at t a = 25 c under nominal cond itions, unless otherwise noted. operating ambient temperature mm912x634xmxxx mm912x634xvxxx t a -40 to 125 -40 to 105 ? c operating junction temperature - analog die t j_a -40 to 150 ? c operating junction temperature - mcu die t j_m -40 to 150 ? c table 10. supply currents ratings symbol min typ (14) max unit normal mode analog die only, excluding external loads, lin recessive state (5.5 v ? v sup ? 18 v, 2.25 v ? v dd ? 2.75 v, 4.5 v ? v ddx ? 5.5v, -40c ? t j_a ? 150 c). i run_a -5.08.0ma normal mode mcu die only (t j_m =150 c; v ddd2d = 2.75 v, v ddrx = 5.5 v, f osc = 4.0 mhz, f bus = f busmax (15)(16) i run_m -1820ma stop mode internal analog die only, excl uding external loads, lin recessive state, lx enabled, measured at vs1+vs2 (5.5 v ? v sup ? 18 v, 2.25 v ? v dd ? 2.75 v, 4.5 v ? v ddx ? 5.5 v) -40 c ? t j_a ? 125 c i stop_a -2040 a stop mode mcu die only (v ddd2d = 2.75 v, v ddrx = 5.5 v, f osc = 4.0 mhz; mcu in stop; rti and cop off) (17) t j_m =150c t j_m =-40c t j_m =25c i stop_m - - - 85 31 31 150 50 50 a sleep mode (vdd = vddx = off; 5.5 v ? v sup ? 18 v; -40 c ? t j_a ? 125 c; 3.0 v ? l x ? 1.0 v). i sleep -1528a cyclic sense suppl y current adder (5.0 ms cycle) i cs -1520a note: 14. typical values noted reflect the approximate parameter mean at t a = 25 c 15. f busmax frequency ratings differ by device and is specified in table 1 16. i run_m denotes the sum of the currents flowing into vdd and vddx. 17. i stop_m denotes the sum of the currents flowing into vdd and vddx. table 9. operating conditions ratings symbol value unit
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 16 3.5.1 static electrical characteristics analog die table 11. static electrical ch aracteristics - power supply ratings symbol min typ max unit power-on reset (por) threshold (measured on vs1) v por 1.5 - 3.5 v low voltage warning (lvi) threshold (measured on vs1, falling edge) hysteresis (measured on vs1) v lvi v lvi_h 5.55 - 6.0 1.0 6.6 - v high voltage warning (hvi) threshold (measured on vs2, rising edge) hysteresis (measured on vs2) v hvi v hvi_h 18 - 19.25 1.0 20.5 - v low battery warning (lbi) threshold (measured on vsense, falling edge) hysteresis (measured on vsense) v lbi v lbi_h 5.55 - 6.0 1.0 6.6 - v j2602 under-voltage threshold v j2602uv 5.5 5.7 6.2 v low vddx voltage (lvrx) threshold v lvrx 2.7 3.0 3.3 v low vdd voltage reset (lvr) threshold normal mode v lvr 2.30 2.35 2.4 v low vdd voltage reset (lvr) threshold stop mode v lvrs 1.6 1.85 2.1 v vdd over-voltage threshold (vrov) v vddov 2.575 2.7875 3.0 v vddx over-voltage threshold (vrovx) v vddxov 5.25 5.675 6.1 v table 12. static electrica l characteristics - resets ratings symbol min typ max unit low-state output voltage i out = 2.0 ma v ol --0.8v pull-up resistor r rpu 25 - 50 kohm low-state input voltage v il - - 0.3v ddx v high-state input voltage v ih 0.7v ddx --v reset release voltage (vddx) v rstrv -1.5- v reset_a pin current limitation 5.0 7.5 10 ma table 13. static electrical char acteristics - window watchdog ratings symbol min typ max unit watchdog disable voltage (fixed voltage) v tst 7.0 - 10 v watchdog enable voltage (fixed voltage) v tsten --5.5v table 14. static electrical characteris tics - voltage regulator 5.0 v (vddx) ratings symbol min typ max unit normal mode output voltage 1.0 ma < i vddx + i vddxinternal < 80 ma; 5.5 v < v sup < 27 v v ddxrun 4.75 5.00 5.25 v normal mode output current limitation (i vddx )i vddxrun 80 130 200 ma stop mode output voltage (i vddx < 500 a) v ddxstop -5.05.5v stop mode output current limitation (i vddx )i vddxstop 1.0 - 20 ma line regulation normal mode, i vddx = 80 ma stop mode, i vddx = 500 a lr xrun lr xstop - - 20 - 25 200 mv
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 17 load regulation normal mode, 1.0 ma < i vddx < 80 ma normal mode, v sup = 3.6 v, 1.0 ma < i vddx < 40 ma stop mode, 0.1 ma < i vddx < 500 a ld xrun ld xcrk ld xstop - - - 15 - - 80 200 250 mv external capacitor c vddx 1.0 - 10 f external capacitor esr c vddx_r --10ohm table 15. static electrical characteris tics - voltage regulator 2.5 v (vdd) ratings symbol min typ max unit normal mode output voltage 1.0 ma < i vdd <= 45 ma; 5.5 v < v sup < 27 v v ddrun 2,425 2.5 2,575 v normal mode output current limitation (i vdd ) t j < 25 c t j 25 c i vddlimrun - - 80 80 120 143 ma stop mode output voltage (i vdd < 0.5 ma) v ddstop 2.25 2.5 2.75 v stop mode output current limitation (i vdd )i vddlimstop --10ma line regulation normal mode, i vdd = 45 ma stop mode, i vdd = 1.0 ma lr run lr stop - - 10 - 12.5 200 mv load regulation normal mode, 1.0 ma < i vdd < 45 ma normal mode, v sup = 3.6 v, 1.0 ma < i vdd < 30 ma stop mode, 0.1 ma < i vdd < 1.0 ma ld run ld crk ld stop - - - 7.5 - - 40 40 200 mv external capacitor c vdd 1.0 - 10 f external capacitor esr c vdd_r --10ohm table 16. static electrical characteristi cs - hall sensor supply output - hsup ratings symbol min typ max unit current limitation i hsup 40 70 90 ma output drain-to-source on resistance t j = 150 c, iload = 30 ma; 5.5 v vsup 16 v t j = 150 c, iload = 30 ma; 3.7 v vsup < 5.5 v r ds(on) - - - - 10 12 ohm output voltage: (18 v ? v sup ? 27 v) vhsup max 16 17.5 18 v load regulation (1.0 ma < i hsup < 30 ma; v sup > 18 v) ld hsup - - 500 mv hall supply capacitor range c hsup 0.22 - 10 f external capacitor esr c hsup_r --10ohm table 14. static electrical characteris tics - voltage regulator 5.0 v (vddx) ratings symbol min typ max unit
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 18 table 17. static electrical charact eristics - high side drivers - hs ratings symbol min typ max unit output drain-to-source on resistance t j = 25 c, i load = 50 ma; v sup > 9.0 v t j = 150 c, i load = 50 ma; v sup > 9.0 v t j = 150 c, i load = 30 ma; 5.5 v < v sup < 9.0 v r ds(on) - - - - - - 7.0 10 14 ohm output current limitation (0 v < v out < v sup - 2.0 v) i limhsx 60 110 250 ma open load current detection i olhsx -5.07.5ma leakage current (-0.2 v < v hsx < v s2 + 0.2 v) i leak --10a current limitation flag threshold (5.5 v < v sup < 27 v) v thsc v sup -2 - - v table 18. static electrical charact eristics - low side drivers - ls ratings symbol min typ max unit output drain-to-source on resistance t j = 25 c, i load = 150 ma, v sup > 9.0 v t j = 150 c, i load = 150 ma, v sup > 9.0 v t j = 150 c, i load = 120 ma, 5.5 v < v sup < 9.0 v r ds(on) ? ? ? ? ? ? 2.5 4.5 10 ohm output current limitation (2.0 v < v out < v sup )i limlsx 180 275 380 ma open load current detection i ollsx -8.012ma leakage current (-0.2 v < v out < vs1) i leak --10a active output energy clamp (i out = 150 ma) v clamp 40 - 45 v coil series resistance (i out = 150 ma) r coil 120 - ohm coil inductance (i out = 150 ma) r coil --400m ? current limitation flag threshold (5.5 v < v sup < 27 v) v thsc 2.0 - - v table 19. static electrical characteristics - lin physi cal layer interface - lin ratings symbol min typ max unit current limitation for driver dominant state. v bus = 18 v i buslim 40 120 200 ma input leakage current at the receiver incl. pull-up resistor rslave; driver off; v bus = 0 v; v bat = 12 v i bus_pas_dom -1.0 - - ma input leakage current at the receiver incl. pull-up resistor rslave; driver off; 8.0 v < v bat < 18 v; 8.0 v < v bus < 18 v; v bus ? v bat i bus_pas_rec --20a input leakage current; gnd disconnected; gnddevice = vsup; 0 < v bus < 18 v; v bat = 12 v i bus_no_gnd -1.0 - 1.0 ma input leakage current; vbat disconnected; vsup_device = gnd; 0 < v bus < 18 v ibus_no_bat - - 100 a receiver input voltage; receiver dominant state v busdom --0.4v sup receiver input voltage; receiver recessive state v busrec 0.6 - - v sup receiver threshold center (v th_dom + v th_rec )/2 v bus_cnt 0.475 0.5 0.525 v sup receiver threshold hysteresis (v th_rec - v th_dom )v bus_hys - - 0.175 v sup voltage drop at the serial diode d ser_int 0.4 0.7 1.0 v lin pull-up resistor r slave 20 30 60 kohm bus wake-up threshold from stop or sleep v wup 4.0 5.0 6.0 v bus dominant voltage v dom --2.5v
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 19 table 20. static electrical characte ristics - high voltage inputs - lx ratings symbol min typ max unit low detection threshold (7.0 v ? v sup ? 27 v) (5.5 v ? v sup ? 7.0 v) v thl 2.2 1.5 2.5 2.5 3.4 4.0 v high detection threshold (7.0 v ? v sup ? 27 v) (5.5 v ? v sup ? 7.0 v) v thh 2.6 2.0 3.0 3.0 3.7 4.5 v hysteresis (5.5 v < v sup < 27 v) v hys 0.25 0.45 1.0 v input current lx (-0.2 v < v in < vs1) i in -10 - 10 a analog input impedance lx r lxin --1.2mohm lx series resistor r lx 9.5 10 10.5 kohm lx capacitor (optional) (18) c lx - 100 - nf analog input divider ratio (ratio lx = v lx / v adout0 ) lxds (lx divider select) = 0 lxds (lx divider select) = 1 ratio lx - - 2.0 7.2 - - analog input divider ratio accuracy ratio lx -5.5 - 5.5 % analog inputs channel ratio - mismatch lxds (lx divider select) = 0 lxds (lx divider select) = 1 lx match - - - - 5.0 5.0 % note: 18. the esd behavior specified in section 3.8, ?esd protection and latch-up immunity are guaranteed without the optional capacitor. table 21. static electrical characteri stics - general purpose i/o - ptb[0?2] ratings symbol min typ max unit input high voltage v ih 0.7v ddx -v ddx +0.3 v input low voltage v il v ss -0.3 - 0.35v ddx v input hysteresis v hys - 140 - mv input high voltage (vs1 = 3.7 v) v ih3.7 2.1 - v ddx +0.3 v input low voltage (vs1 = 3.7 v) v il3.7 v ss -0.3 - 1.4 v input hysteresis (vs1 = 3.7 v) v hys3.7 100 200 300 mv input leakage current (pins in high-impedance input mode) (v in = v ddx or v ssx ) i in -1.0 - 1.0 a output high voltage (pins in output mode) full drive i oh = -10 ma v oh v ddx -0.8 - - v output low voltage (pins in output mode) full drive i ol = 10 ma v ol --0.8v internal pull-up resistance (v ih min > input voltage > v il max) r pul 26.25 37.5 48.75 kohm input capacitance c in -6.0- pf clamp voltage when selected as analog input v cl_ain vdd - - v analog input impedance = 10 kohm max, capacitance = 12 pf r ain - - 10 kohm analog input capacitance = 12 pf c ain -12- pf maximum current all ptb combined (vddx capability!) i bmax -15 - 15 ma output drive strength at 10 mhz c out - - 100 pf
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 20 table 22. static electrical characterist ics - analog digital converter - adc (19) ratings symbol min typ max unit adc2p5 reference voltage 5.5 v < v sup < 27 v v adc2p5ru n 2,45 2.5 2.55 v adc2p5 reference stop mode output voltage v adc2p5st op - - 100 mv line regulation, normal mode lr runa - 10 12.5 mv external capacitor c adc2p5 0.1 - 1.0 f external capacitor esr c vdd_r --10ohm scale factor error e scale -1 - 1 lsb differential linearity error e dnl -1.5 - 1.5 lsb integral linearity error e inl -1.5 - 1.5 lsb zero offset error e off -2.0 - 2.0 lsb quantization error e q -0.5 - 0.5 lsb total error with offset compensation te -5.0 - 5.0 lsb bandgap measurement channel (ch14) valid result range (including 7.0% bg1p25sleep accuracy + high-impedance measurement error of 5.0% at f adc ) (20) ad ch14 1.11.251.4 v note: 19. no external load allowed on the adc2p5 pin. 20. reduced adc frequency will lower measurement error. table 23. static electric al characteristics - current sense module - isense ratings symbol min typ max unit gain csgs (current sense gain select) = 000 csgs (current sense gain select) = 001 csgs (current sense gain select) = 010 csgs (current sense gain select) = 011 csgs (current sense gain select) = 100 csgs (current sense gain select) = 101 csgs (current sense gain select) = 110 csgs (current sense gain select) = 111 g - - - - - - - - 7 9 10 12 14 18 24 36 - - - - - - - - gain accuracy -3.0 - 3.0 % offset -1.5 - 1.5 % resolution (21) res - 51 - ma/lsb isenseh, isensel input common mode voltage range v in -0.2 - 3.0 v current sense module - normal mode current consumption adder (cse = 1) i isense - 600 - a note: 21. res = 2.44 mv/(gain*r shunt ) table 24. static electric al characteristics - temperature sensor - tsense ratings symbol min typ max unit internal chip temperature sense gain (22) ts g -9.17-mv/k internal chip temperature sense error at the end of conversion (22) ts err ?5.0 - 5.0 c temperature represented by a adc in voltage of 0.150 v (22) t 0.15v -55 -50 -45 c
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 21 3.5.2 static electrical characteristics mcu die 3.5.2.1 i/o characteristics this section describes the characte ristics of all i/o pins except extal, xtal, test and supply pins. temperature represented by a adc in voltage of 1.984 v (22) t 1.984v 145 150 155 c note: 22. guaranteed by design and characterization. table 25. static electrical ch aracteristics - supp ly voltage sense - vsense and vs1sense ratings symbol min typ max unit vsense input divider ratio (ratio vsense = v vsense / adcin) 5.5 v < v sup < 27 v ratio vsens e - 10.8 5.0% vsense error - whole path (vsense pad to digital value) er vsense --5.0% vs1sense input divider ratio (ratio vs1sense = v vs1sense / adcin) 5.5 v < v sup < 27 v ratio vs1se nse - 10.8 5.0% vs1sense error - whole path (vs1 pad to digital value) er vs1sense --5.0% vsense series resistor r vsense 9.5 10 10.5 kohm vsense capacitor (optional) (23) c vsense - 100 - nf note: 23. the esd behavior specified in section 3.8, ?esd protection and latch-up immunity is guaranteed without the optional capacitor. table 26. 5.0 v i/o character istics for pta, pte, reset and bkgd pins ratings symbol min typ max unit input high voltage v ih 0.65*v ddrx --v input high voltage v ih -- v ddrx + 0.3 v input low voltage v il -- 0.35*v ddr x v input low voltage v il v ssrx - 0.3 - - v input hysteresis v hys - 250 - mv input leakage current (pins in high-impedance input mode) v in = v ddrx or v ssrx i in -1.0 - 1.0 ? a output high voltage (pins in output mode) i oh = -4.0 ma v oh v ddrx ? 0.8 - - v output low voltage (pins in output mode) i ol = +4.0 ma v ol --0.8v internal pull-up resistance (v ih min > input voltage > v il max) r pul 25 - 50 k ? internal pull-down resistance (v ih min > input voltage > v il max) r pdh 25 - 50 k ? input capacitance c in -6.0-pf injection current (24) single pin limit total device limit, sum of all injected currents i ics i icp -2.5 -25 - - 2.5 25 ma note: 24. refer to section 3.8, ?esd protection and latch-up immunity ? for more details. table 24. static electric al characteristics - temperature sensor - tsense ratings symbol min typ max unit
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 22 3.5.2.2 electrical specification for mcu internal voltage regulator note the lvr monitors the voltages v dd_core , v ddflash and v ddrx . as soon as voltage drops on these supplies which would prohibit the correct function of the microcontroller, the lvr is triggering a reset. 3.5.2.3 chip power-up and voltage drops lvi (low voltage interrupt), por (power-on reset) and lvrs (low voltage reset) handle chip power-up or drops of the supply voltage. figure 4. mc9s12i32 - chip power-up and voltage drops (not scaled) table 27. ivreg characteristics characteristic symbol min typical max unit vddrx low voltage reset (25)(26)(27) assert level deassert level v lvrxa v lvrxd 2.97 ? 3.06 3.09 ? 3.3 v v power-on reset (28) assert level deassert level v pora v pord 0.6 ? 0.9 0.95 ? 1.60 v v note: 25. device functionality is guaranteed on power down to the lvr assert level. 26. monitors vddrx, active only in full performanc e mode. mcu is monitored by the por in rpm (see figure ). 27. monitors vddrx, active only in full performance mode. v lvra and v pord . 28. monitors mcu_core_vdd . active in all modes. v lvid v lvia v lvrd v lvra v pord lvi por lvr t v v ddrx v dd_core lvi enabled lvi disabled due to lvr
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 23 3.6 dynamic electrical characteristics dynamic characteristics noted under conditions 5.5 v ? v sup ? 18 v, -40 c ? t a ?? 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. 3.6.1 dynamic electrical characteristics analog die table 28. dynamic electrical characteristics - modes of operation ratings symbol min typ max unit vdd short timeout t vto 110 150 205 ms analog base clock f base - 100 - khz reset delay t rst 140 200 280 s table 29. dynamic electrical characteristics - power supply (29) ratings symbol min typ max unit glitch filter low battery warning (lbi) t lb -2.0- s glitch filter low voltage warning (lvi) t lv -2.0- s glitch filter high voltage warning (hvi) t hv -2.0- s note: 29. guaranteed by design. table 30. dynamic electrical characte ristics - die to die interface - d2d ratings symbol min typ max unit operating frequency (d2dclk, d2d[0:3]) f d2d -- f busmax (30 ) mhz note: 30. f busmax frequency ratings differ by device and is specified in table 1 table 31. dynamic electrical characteristics - resets ratings symbol min typ max unit reset deglitch filter time t rstdf 1.2 2.0 3.0 s reset low level duration t rstlow 140 200 280 s table 32. dynamic electrical characte ristics - wake-up / cyclic sense ratings symbol min typ max unit lx wake-up filter time t wuf -20 ? s cyclic sense / forced wake-up timing accuracy - not trimmed cs ac -35 - 35 % cyclic sense / forc ed wake-up timing accuracy - trimmed (31) cs act -5.0 - 5.0 % time between hsx on and lx sense during cyclic sense t s same as t hson / t hsont - hsx on duration during cyclic sense t hson 140 200 280 ? s hsx on duration during cyclic sense - trimmed (31) t hsont 180 200 220 ? s note: 31. no trimming possible in sleep mode.
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 24 table 33. dynamic electrical ch aracteristics - window watchdog ratings symbol min typ max unit initial non-window watchdog timeout t iwdto 110 150 190 ms watchdog timeout accuracy - not trimmed wd ac -35 - 35 % watchdog timeout accuracy - trimmed wd act -5.0 - 5.0 % table 34. dynamic electrical characte ristics - high side drivers - hs ratings symbol min typ max unit high side operating frequency (32) load condition: c load ??? 2.2 nf; r load ??? 500 ? f hs --50 khz note: 32. guaranteed by design. table 35. dynamic electrical charac teristics - low side drivers - ls ratings symbol min typ max unit low side operating frequency f ls --10khz table 36. dynamic electrical characteristi cs - lin physical layer interface - lin ratings symbol min typ max unit bus wake-up deglitcher (sleep and stop mode) t propwl 60 80 100 s fast bit rate (programming mode) br fast - - 100 kbit/s propagation delay of receiver, t rec_pd = max (t rec_pdr , t rec_pdf ) (33) t rec_pd --6.0s symmetry of receiver propagation delay, t rec_pdf - t rec_pdr t rec_sym -2.0 - 2.0 s lin driver - 20.0 kbit/s; bus load conditions (c bus ; r bus ): 1.0nf; 1.0k ? / 6,8 nf;660 ? / 10 nf;500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 5 and figure 6 . duty cycle 1: th rec(max) = 0.744 x v sup th dom(max) = 0.581 x v sup 7.0 v ?? v sup ??? 18 v; t bit = 50 s; d1 = t bus_rec(min) /(2 x t bit ) d1 0.396 - - note: 33. v sup from 7.0 to 18 v, bus load r bus and c bus 1.0nf / 1.0k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 5 and figure 8 . duty cycle 2: th rec(min) = 0.422 x v sup th dom(min) = 0.284 x v sup 7.6 v ?? v sup ??? 18 v; t bit = 50 s d2 = t bus_rec(max) /(2 x t bit ) d2 - - 0.581 lin driver - 10.0 kbit/s; bus load conditions (c bus ; r bus ): 1.0 nf; 1.0 k ? / 6,8 nf;660 ? / 10 nf;500 ?? measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 5 and figure 7 . duty cycle 3: th rec(max) = 0.778 x v sup th dom(max) = 0.616 x v sup 7.0 v ?? v sup ??? 18 v; t bit = 96 s d3 = t bus_rec(min) /(2 x t bit ) d3 0.417 - -
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 25 figure 5. test circuit for timing measurements figure 6. lin timing measur ements for normal baud rate duty cycle 4: th rec(min) = 0.389 x v sup th dom(min) = 0.251 x v sup 7.6 v ?? v sup ??? 18 v; t bit = 96 s d4 = t bus_rec(max) /(2 x t bit ) d4 - - 0.590 lin transmitter timing, (v sup from 7.0 to 18 v) - see figure 9 transmitter symmetry ttran_sym < max(ttran_sym60%, ttran_sym40%) tran_sym60% = ttran_pdf60% - ttran_pdr60% tran_sym40% = ttran_pdf40% - ttran_pdr40% ttran_sym -7.25 0 7.25 s table 36. dynamic electrical characteristi cs - lin physical layer interface - lin ratings symbol min typ max unit
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 26 figure 7. lin timing measurements for slow baud rate figure 8. lin receiver timing figure 9. lin transmitter timing bus tx 60% 40% ttran_pdr60% ttran_pdr40% ttran_pdf60% ttran_pdf40%
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 27 3.6.2 dynamic electrical characteristics mcu die 3.6.2.1 nvm 3.6.2.1.1 timing parameters the time base for all nvm program or erase operations is deriv ed from the bus clock using the fclkdiv register. the frequency of this derived clock must be se t within the limits specified as f nvmop . the nvm module does not have any means to monitor the frequency and will not prevent program or erase operations at frequencies above or below the specified minimum. when attempting to program or erase the nvm module at a lower frequency, a full prog ram or erase transition is not assured. the following sections provide equations which can be used to det ermine the time required to ex ecute specific flash commands. all timing parameters are a function of the bus clock frequency, f nvmbus . all program and erase times are also a function of the nvm operating frequency, f nvmop . a summary of key timing parameters can be found in table . 3.6.2.1.1.1 erase verify all bl ocks (blank check) (fcmd=0x01) the time required to perform a blank check on all blocks is dependen t on the location of the first non-blank word starting at r elative address zero. it takes one bus cycle per phrase to verify plus a setup of the comm and. assuming that no non-blank location is found, then the time to erase verify all blocks is given by: 3.6.2.1.1.2 erase verify bl ock (blank check) (fcmd=0x02) the time required to perform a blank check is dependent on the lo cation of the first non-blank word starting at relative addres s zero. it takes one bus cycle per phrase to verify plus a setup of the command. assuming that no non-blank location is found, then the time to erase verify a p-flash block is given by: assuming that no non-blank location is found, then the time to erase verify a d-flash block is given by: table 37. dynamic electrical characteri stics - general purpose i/o - ptb[0?2] (34) ratings symbol min typ max unit gpio digital frequency f ptb --10mhz propagation delay - rising edge (35) t pdr - - 20 ns rise time - rising edge (34) t rise --17.5ns propagation delay - falling edge (34) t pdf - - 20 ns rise time - falling edge (34) t fall --17.5ns note: 34. guaranteed by design. 35. load ptbx = 100 pf. table 38. dynamic electrical characteris tics - analog digi tal converter - adc (36) ratings symbol min typ max unit adc operating frequency f adc 1.6 2.0 2.4 mhz conversion time (from accr write to cc flag) t conv 26 clk sample frequency channel 14 (bandgap) f ch14 --2.5khz note: 36. guaranteed by design. t check 19200 1 f nvmbus ------------------- - ? = t pcheck 17200 1 f nvmbus ------------------- - ? =
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 28 3.6.2.1.1.3 erase verify p-flash section (fcmd=0x03) the maximum time to erase verify a section of p-flas h depends on the number of phrases being verified (n vp ) and is given by: 3.6.2.1.1.4 read once (fcmd=0x04) the maximum read once time is given by: 3.6.2.1.1.5 program p-flash (fcmd=0x06) the programming time for a single phrase of four p-flash words and the two seven-bit ecc fields is dependent on the bus frequency, f nvmbus , as well as on the nvm operating frequency, f nvmop . the typical phrase programming time is given by: the maximum phrase programming time is given by: 3.6.2.1.1.6 program once (fcmd=0x07) the maximum time required to program a p-flash program once field is given by: 3.6.2.1.1.7 erase all blocks (fcmd=0x08) the time required to erase all blocks is given by: 3.6.2.1.1.8 erase p-fl ash block (fcmd=0x09) the time required to erase the p-flash block is given by: t dcheck 2800 1 f nvmbus ------------------- - ? = t 450 n vp + ?? 1 f nvmbus ------------------- - ? ? t 400 1 f nvmbus ------------------- - ? = t ppgm 164 1 f nvmop ----------------- 2000 1 f nvmbus ------------------- - ? + ? ? t ppgm 164 1 f nvmop ----------------- 2500 1 f nvmbus ------------------- - ? + ? ? t 164 1 f nvmop ----------------- 2150 1 f nvmbus ------------------- - ? + ? ? t mass 100100 1 f nvmop ----------------- 38000 1 f nvmbus ------------------- - ? + ? ? t pmass 100100 1 f nvmop ----------------- 35000 1 f nvmbus ------------------- - ? + ? ?
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 29 3.6.2.1.1.9 erase p-flash sector (fcmd=0x0a) the typical time to erase a 512-byte p-flash sector is given by: the maximum time to erase a 512-by te p-flash sector is given by: 3.6.2.1.1.10 unsecure flash (fcmd=0x0b) the maximum time required to erase and unsecure the flash is given by: 3.6.2.1.1.11 verify backdo or access key (fcmd=0x0c) the maximum verify back door access key time is given by: 3.6.2.1.1.12 set user ma rgin level (fcmd=0x0d) the maximum set user margin level time is given by: 3.6.2.1.1.13 set field ma rgin level (fcmd=0x0e) the maximum set field margin level time is given by: 3.6.2.1.1.14 erase verify d-flash section (fcmd=0x10) the time required to erase verify d-flash for a given number of words n w is given by: 3.6.2.1.1.15 program d-flash (fcmd=0x11) d-flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, since programming across a row boundary requires extr a steps. the d-flash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary. the typical d-flash programming time is given by the following equation, where n w denotes the number of words; bc=0 if no row boundary is crossed and bc=1 if a row boundary is crossed: t pera 20020 1 f nvmop ----------------- ? 700 1 f nvmbus ------------------- - ? + ? t pera 20020 1 f nvmop ----------------- ? 1400 1 f nvmbus ------------------- - ? + ? t uns 100100 1 f nvmop ----------------- 38000 1 f nvmbus ------------------- - ? + ? ? t 400 1 f nvmbus ------------------- - ? = t 350 1 f nvmbus ------------------- - ? = t 350 1 f nvmbus ------------------- - ? = t dcheck 450 n w + ?? 1 f nvmbus ------------------- - ? ? t dpgm 14 54 n w ? ?? + ? 14 bc ? ??? + 1 f nvmop ----------------- ? ? ? ? ? 500 525 n w ? ?? 100 bc ? ?? ++ ?? 1 f nvmbus ------------------- - ? ? ? ? ? + ?
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 30 the maximum d-flash programming time is given by: 3.6.2.1.1.16 erase d-fl ash sector (fcmd=0x12) typical d-flash sector erase times, expected on a new dev ice where no margin verify fails occur, is given by: maximum d-flash sector er ase times is given by: the d-flash sector erase time is ~5.0 ms on a new dev ice and can extend to ~20 m s as the flash is cycled. 3.6.2.1.2 nvm reli ability parameters the reliability of the nvm blocks is guaranteed by stress test du ring qualification, constant process monitors, and burn-in to screen early life failures. the data retention and program/erase cycling failure rates are spec ified at the operating conditio ns noted. the program/erase cycle count on the sector is in cremented every time a sector or mass erase event is executed. note all values shown in ta b l e 4 0 are preliminary and subject to further characterization. table 39. nvm timing characteristics (ftmrc) c rating symbol min typ (37) max (38) unit (39) bus frequency (40) f nvmbus 1?32mhz operating frequency f nvmop 0.8 1.0 1.05 mhz d erase all blocks (mass erase) time t mass ? 100 130 ms d erase verify all blocks (blank check) time t check ? ? 19200 t cyc d unsecure flash time t uns ? 100 130 ms d p-flash block erase time t pmass ? 100 130 ms d p-flash erase verify (blank check) time t pcheck ? ? 17200 t cyc d p-flash sector erase time t pera ?2026ms d p-flash phrase programming time t ppgm ? 226 285 ? s d d-flash sector erase time t dera ?5 (41) 26 ms d d-flash erase verify (blank check) time t dcheck ? ? 2800 t cyc d d-flash one word programming time t dpgm1 ? 100 107 ? s d d-flash two word programming time t dpgm2 ? 170 185 ? s d d-flash three word programming time t dpgm3 ? 241 262 ? s d d-flash four word programming time t dpgm4 ?311339 ? s d d-flash four word programming time crossing row boundary t dpgm4c ? 328 357 ? s note: 37. typical program and erase times are based on typical f nvmop and maximum f nvmbus . 38. maximum program and erase times are based on minimum f nvmop and maximum f nvmbus . 39. t cyc = 1 / f nvmbus 40. the maximum device bus clo ck is specified as fbus. 41. typical value for a new device. t dpgm 14 54 n w ? ?? + ? 14 bc ? ??? + 1 f nvmop ----------------- ? ? ? ? ? 500 750 ? n w ? ? 100 bc ? ?? ++ ?? 1 f nvmbus ------------------- - ? ? ? ? ? + ? t dera 5025 1 f nvmop ----------------- 700 1 f nvmbus ------------------- - ? + ? ? t dera 20100 1 f nvmop ----------------- 3400 1 f nvmbus ------------------- - ? + ? ?
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 31 3.6.2.2 phase locked loop 3.6.2.2.1 jitte r definitions with each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously wit h no abrupt changes in the vcoclk frequency. noise, voltage, temperature, and other factors caus e slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods, as illustrated in figure 10 . figure 10. jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). jitter is defined as: table 40. nvm reliability characteristics rating symbol min typ max unit program flash arrays data retention at an average junction temperature of t javg = 85 ? c (42) after up to 10,000 program/erase cycles t nvmret 20 100 (43) ? years program flash number of program/erase cycles (-40 ? c ? t j ? 150 ? c ? n flpe 10k 100k (44) ?cycles data flash array data retention at an average junction temperature of t javg = 85 ? c (42) after up to 50,000 program/erase cycles t nvmret 5 100 (43) ? years data retention at an average junction temperature of t javg = 85 ? c (42) after up to 10,000 program/erase cycles t nvmret 10 100 (43) ? years data retention at an average junction temperature of t javg = 85 ? c (42) after less than 100 program/erase cycles t nvmret 20 100 (43) ? years data flash number of program/erase cycles (-40 ? c ? t j ? 150 ? c ? n flpe 50k 500k (44) ?cycles note: 42. t javg does not exceed 85 ? c in a typical temperature profile over the lifetime of a consumer, industria l or automotive application. 43. typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 ? c using the arrhenius equation. for additional in formation on how freescale defines typical data retention, please refer to engin eering bulletin eb618 44. spec table quotes typical endurance evaluated at 25 ? c for this product family. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619. 23 n-1n 1 t nom t max1 t min1 t maxn t minn 0 jn ?? max 1 t max n ?? nt nom ? ----------------------- ? 1 t min n ?? nt nom ? ---------------------- - ? , ?? ?? ?? =
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 32 for n < 100, the following equation is a good fit for the maximum jitter: figure 11. maximum bus clock jitter approximation note on timers and serial modules a prescaler will elim inate the effect of the jitter to a large extent. 3.6.2.2.2 electri cal characteristics for the pll (45) 3.6.2.3 electrical characteristics for the irc1m table 41. pll characteristics rating symbol min typ max unit vco frequency during system reset f vcorst 8.0 ? 32 mhz vco locking range f vco 32 ? 64 mhz reference clock f ref 1.0 ? ? mhz lock detection ?? lock |0 ? 1.5% (46) un-lock detection ?? unl | 0.5 ? 2.5 % (46) time to lock t lock ?? 150 + 256/f ref ? s jitter fit parameter 1 (47) j 1 ??1.2% note: 45. the maximum device bus cloc k is specified as fbus. 46. % deviation from target frequency. 47. f ref = 1.0 mhz, f bus = 32 mhz equivalent f pll = 64 mhz, refrq=00, syndiv=$1f, vcofrq=01, postdiv=$00. table 42. irc1m characteristics rating symbol min typ max unit internal reference frequency, factory trimmed -40 c ? t j ? 150 c f irc1m_trim 0.987 1.0 1.013 mhz jn ?? j 1 n ------- - = 1 5 10 20 n j(n)
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 33 3.6.2.4 electrical characteristics for the oscillator (osclcp) 3.6.2.5 reset characteristics 3.6.2.6 spi timing this section provides electrical pa rametrics and ratings for the spi. in ta b l e 4 5 the measurement conditions are listed. 3.6.2.6.1 master mode in figure 12 the timing diagram for master mode with transmission format cpha = 0 is depicted. table 43. osclcp characteristics rating symbol min typ max unit crystal oscillator range f osc 4.0 ? 16 mhz startup current i osc 100 ? ? ? a oscillator start-up time (lcp, 4mhz) (48) t uposc ?2.010 ms oscillator start-up time (lcp, 8mhz) (48) t uposc ?1.68.0 ms oscillator start-up time (lcp, 16mhz) (48) t uposc ?1.05.0 ms clock monitor failure assert frequency f cmfa 200 450 1200 khz input capacitance (extal, xtal pins) c in ?7.0? pf extal pin input hysteresis v hys,extal ?120? mv extal pin oscillation amp litude (loop controlled pierce) v pp,extal ?0.9? v note: 48. these values apply for carefully designed pcb layouts with capacitors that match the cr ystal/resonator requirements. 49. only applies if extal is externally driven. table 44. reset and stop characteristics rating symbol min typ max unit reset input pulse width, minimum input time pw rstl 2.0 ? ? t vcorst startup from reset n rst ? 768 ? t vcorst stop recovery time t stp_rec ?50? ? s table 45. measurement conditions description value unit drive mode full drive mode ? load capacitance c load (50) , on all outputs 50 pf thresholds for delay measurement points (20% / 80%) v ddrx v note: 50. timing specified for equal load on all sp i output pins. avoid asymmetric load.
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 34 figure 12. spi master timing (cpha = 0) in figure 13 the timing diagram for master mode with transmission format cpha=1 is depicted. figure 13. spi master timing (cpha = 1) in ta b l e 4 6 the timing characteristics for master mode are listed. sck (output) sck (output) miso (input) mosi (output) ss (output) 1 9 5 6 msb in2 bit msb-1 ? 1 lsb in msb out2 lsb out bit msb-1? 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1. if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, bit 2... msb. 12 12 sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in2 bit msb-1... 1 lsb in master msb out2 master lsb out bit msb-1... 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss (output) 2 12 13 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1,bit 2... msb.
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 35 3.6.2.6.2 slave mode in figure 14 the timing diagram for slave mode with transmission format cpha = 0 is depicted. figure 14. spi slave timing (cpha = 0) in figure 15 the timing diagram for slave mode with transmission format cpha = 1 is depicted. table 46. spi master mode timing characteristics characteristic symbol min typ max unit sck frequency f sck 1/2048 ? 1 ? 2f bus sck period t sck 2.0 ? 2048 t bus enable lead time t lead ?1/2?t sck enable lag time t lag ?1/2?t sck clock (sck) high or low time t wsck ?1/2?t sck data setup time (inputs) t su 8.0 ? ? ns data hold time (inputs) t hi 8.0 ? ? ns data valid after sck edge t vsck ? ? 29 ns data valid after ss fall (cpha = 0) t vss ? ? 15 ns data hold time (outputs) t ho 20 ? ? ns rise and fall time inputs t rfi ??8.0ns rise and fall time outputs t rfo ??8.0ns sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit msb-1... 1 lsb in slave msb slave lsb out bit msb-1... 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not defined 12 12 11 see 13 note 8 10 see note
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 36 figure 15. spi slave timing (cpha = 1) in ta b l e 4 7 the timing characteristics for slave mode are listed. 3.7 thermal protection characteristics characteristics noted under conditions 5.5 v ? v sup ? 18 v, -40 c ? t a ?? 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. table 47. spi slave mode timing characteristics characteristic symbol min typ max unit sck frequency f sck dc ? 1 ? 4f bus sck period t sck 4? ? t bus enable lead time t lead 4? ? t bus enable lag time t lag 4.0 ? ? t bus clock (sck) high or low time t wsck 4.0 ? ? t bus data setup time (inputs) t su 8.0 ? ? ns data hold time (inputs) t hi 8.0 ? ? ns slave access time (time to data active) t a ?? 20 ns slave miso disable time t dis ?? 22 ns data valid after sck edge t vsck ? ? 29 + 0.5 ? t bus (51) ns data valid after ss fall t vss ? ? 29 + 0.5 ? t bus (51) ns data hold time (outputs) t ho 20 ? ? ns rise and fall time inputs t rfi ?? 8.0 ns rise and fall time outputs t rfo ?? 8.0 ns note: 51. 0.5 t bus added due to internal synchronization delay sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit msb-1... 1 lsb in msb out slave lsb out bit msb-1? 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not defined slave 7 8 see note
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 37 3.8 esd protection a nd latch-up immunity all esd testing is in conformity with cdf- aec-q100 stress test qualificat ion for automotive grade int egrated circuits. during t he device qualification, esd stresses were performed for the hu man body model (hbm), machine model (mm), charge device model (cdm), as well as lin tran sceiver specific specifications. a device will be defined as a failure if after exposure to esd pulses, the device no longer meets the device specification. complete dc parametric and functional te sting is performed per the applicable device specificati on at room temperature, followed by hot temperature, unless specified otherwise in the device specification. table 48. thermal characteristics - voltag e regulators vdd (2.5 v) & vddx (5.0 v) (52) ratings symbol min typ max unit vdd/vddx high-temperature warning (hti) threshold hysteresis t hti t hti_h 110 - 125 10 140 - c vdd/vddx over-temperature shutdown threshold hysteresis t sd t sd_h 155 - 170 10 185 - c hsup over-temperature shutdown t hsupsd 150 165 180 c hsup over-temperature shutdown hysteresis t hsupsd_hys -10-c hs over-temperature shutdown t hssd 150 165 180 c hs over-temperature shutdown hysteresis t hssd_hys -10-c ls over-temperature shutdown t lssd 150 165 180 c ls over-temperature shutdown hysteresis t lssd_hys -10-c lin over-temperature shutdown t linsd 150 165 200 c lin over-temperature shutdown hysteresis t linsd_hys -20-c note: 52. guaranteed by characteriza tion. functionality tested. table 49. esd and latch-up protection characteristics ratings symbol value unit esd - human body model (hbm) following aec-q100 / jesd22-a114 (c zap = 100 pf, r zap = 1500 ? ) - lin (dgnd, pgnd, agnd, and lgnd shorted) - vs1, vs2, vsense, lx - hsx - all other pins v hbm 8000 4000 3000 2000 v esd - charged device model (cdm) following aec-q100, corner pins (1, 12, 13, 24, 25, 36, 37, and 48) all other pins v cdm 750 500 v esd - machine model (mm) following aec-q100 (c zap = 200 pf, r zap =0 ? ), all pins v mm 200 v latch-up current at t a = 125 ? c (53) i lat 100 ma esd gun - lin conformance test specification (55) , unpowered, contact discharge, c zap = 150 pf, r zap = 330 ? . - lin (with or without bus filter c bus =220 pf) - vs1, vs2 with c vs - lx with serial r lx 15000 20000 6000 v
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 38 esd gun - following iec 61000-4-2 test specification (56) , unpowered, contact discharge, c zap = 150 pf, r zap = 330 ? - lin (with or without bus filter c bus =220 pf) - vsense with serial r vsense (54) - vs1, vs2 with c vs - lx with serial r lx 8000 8000 8000 8000 v esd gun - following iso10605 test specification (56) , unpowered, contact discharge, c zap = 150 pf, r zap =2.0k ? - lin (with or without bus filter c bus =220pf) - vsense with serial r vsense (54) - vs1, vs2 with c vs - lx with serial r lx 6000 6000 6000 6000 v esd gun - following iso10605 test specification (56) , powered, contact discharge, c zap = 330 pf, r zap =2.0k ? - lin (with or without bus filter c bus =220 pf) - vsense with serial r vsense (54) - vs1, vs2 with c vs - lx with serial r lx 8000 8000 8000 8000 v note: 53. input voltage limit = -2.5 to 7.5 v. 54. with c vbat (10?100 nf) as part of the battery path. 55. certification available on request 56. tested internally only; certification pending table 49. esd and latch-up protection characteristics (continued) ratings symbol value unit
electrical characteristics mm912_634 advance information, rev. 4.0 freescale semiconductor 39 3.9 additional test in formation iso7637-2 immunity against transients for the lin, lx, and vbat, is specifi ed according to the lin conform ance test specification - secti on lin emc test specification refer to t he lin conformance test certification re port - available as separate document.
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 40 4 functional description and application information 4.1 introduction this chapter describes the mm912_634 dual die device functions on a block by blo ck base. to distinguish between the module location being the mcu die or the analog die, the following symbols are shown on all module cover pages: the documented module is physically located on the analog die. this applies to section 4.3, ?mm912_634 - analog die overview through section 4.26, ?mm912_634 - analog die trimming . the documented module is physically located on the microcontroller die. this applies to section 4.27, ?mm912_634 - mcu die overview through section 4.39, ?serial peripheral interface (s12spiv5) . sections concerning both dies or the comple te device will not have a specific indication. 4.2 device register maps table 50 shows the device register memory map over view for the 64 kbyte mcu die (mc9s12i64). table 50. device register memory map overview address module size (bytes) 0x0000?0x0009 pim (port integration module) 10 0x000a?0x000b mmc (memory map control) 2 0x000c?0x000d pim (port integration module) 2 0x000e?0x000f reserved 2 0x0010?0x0015 mmc (memory map control) 8 0x0016?0x0019 reserved 2 0x001a?0x001b device id register 2 0x001c?0x001e reserved 4 0x001f int (interrupt module) 1 0x0020?0x002f dbg (debug module) 16 0x0030?0x0033 reserved 4 0x0034?0x003f cpmu (clock and power management) 12 0x0040?0x00d7 reserved 152 0x00d8?0x00df d2di (die 2 die initiator) 8 0x00e0?0x00e7 reserved 32 0x00e8?0x00ef spi (serial peripheral interface) 8 0x00f0?0x00ff reserved 32 0x0100?0x0113 ftmrc control registers 20 0x0114?0x011f reserved 12 0x0120?0x017f pim (port integration module) 96 0x0180?0x01ef reserved 112 0x01f0?0x01fc cpmu (clock and power management) 13 0x01fd?0x01ff reserved 3 0x0200-0x02ff d2di (die 2 die init iator, blocking access window) 256 0x0300?0x03ff d2di (die 2 die initiator, non-blocking write window) 256 analog mcu analog mcu
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 41 note reserved register space shown in ta b l e 5 0 is not allocated to any module. this register space is reserved for future use, and will show as grayed areas in tables throughout this document. writing to these locations has no effect. read access to these locations returns zero. 4.2.1 detailed module register maps table 51 to ta b l e 7 3 show the detailed module maps of the mc9s12i64 mcu die. table 51. 0x0000?0x0007 port integration module (pim) map 1 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0000 porta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 w 0x0001 portb r000000 pb1 pb0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddre r000000 ddre1 ddre0 w 0x0004- 0x0009 reserved r00000000 w table 52. 0x000a?0x000b memory map control (mmc) map 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000a reserved r00000000 w 0x000b mode r modc 0000000 w table 53. 0x000c?0x000d port integration module (pim) map 2 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000c pucr r0 bkpue 0000 pdpee 0 w 0x000d rdriv r0000 rdrd rdrc 00 w table 54. 0x000e?0x000f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000e- 0x000f reserved r00000000 w table 55. 0x0010?0x001b memory map control (mmc) map 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0010 reserved r00000000 w
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 42 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r00000000 w 0x0013 mmcctl1 r0000000 ifron w 0x0014 reserved r00000000 w 0x0015 ppage r0000 pix3 pix2 pix1 pix0 w table 56. 0x0016?0x0019 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0016- 0x0019 reserved r00000000 w table 57. 0x001a?0x001b device id register (partidh/partidl) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001a partidh rpartidh w 0x001b partidl rpartidl w table 58. 0x001c?0x001e reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001c- 0x001e reserved r00000000 w table 59. 0x001f interrupt module (int) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001f ivbr r ivb_addr[7:0] w table 60. 0x0020?0x002f debug module (dbg) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0020 dbgc1 r arm 00 bdm dbgbrk 0 comrv wtrig 0x0021 dbgsr r tbf 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r0 tsource 00 trcmod 0 talign w table 55. 0x0010?0x001b memory map control (mmc) map 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 43 0x0023 dbgc2 r000000 abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r tbf 0 cnt w 0x0027 dbgscrx r0000 sc3 sc2 sc1 sc0 w dbgmfr r00000mc2mc1mc0 w 0x0028 dbgactl r sze sz tag brk rw rwe ndb compe w dbgbctl r sze sz tag brk rw rwe 0 compe w dbgcctl r0 0 tag brk rw rwe 0 compe w 0x0029 dbgxah r000000 bit 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7654321bit 0 w 0x002c dbgadh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgadl r bit 7654321bit 0 w 0x002e dbgadhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgadlm r bit 7654321bit 0 w table 61. 0x0030?0x033 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0030- 0x0033 reserved r00000000 w table 62. 0x0034?0x003f clock and power management (cpmu) map 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0034 cpmu synr r vcofrq[1:0] syndiv[5:0] w table 60. 0x0020?0x002f debug module (dbg) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 44 0x0035 cpmu refdiv r reffrq[1:0] 00 refdiv[3:0] w 0x0036 cpmu postdiv r000 postdiv[4:0] w 0x0037 cpmuflg r rtif porf lvrf lockif lock ilaf oscif uposc w 0x0038 cpmuint r rtie 00 lockie 00 oscie 0 w 0x0039 cpmuclks r pllsel pstp 00 pre pce rti oscsel cop oscsel w 0x003a cpmupll r0 0 fm1 fm0 0000 w 0x003b cpmurti r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c cpmucop r wcop rsbck 000 cr2 cr1 cr0 w wrtmask 0x003d reserved r00000000 w 0x003e reserved r00000000 w 0x003f cpmu armcop r00000000 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 63. 0x0040?0x0d7 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0040- 0x00d7 reserved r00000000 w table 64. 0x00d8?0x00df die 2 die initiator (d2di) map 1 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d8 d2dctl0 r d2den d2dcw d2dswai 000 d2dclkdiv[1:0] w 0x00d9 d2dctl1 r d2die 000 timeout[3:0] w 0x00da d2dstat0 r errif ackerf cnclf timef terrf parf par1 par0 w 0x00db d2dstat1 r d2dif d2dbsy 0 00000 w 0x00dc d2dadrhi r rwb sz8 0 nblk0000 w 0x00dd d2dadrlo r adr[7:0] w table 62. 0x0034?0x003f clock and power management (cpmu) map 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 45 0x00de d2ddatahi r data[15:8] w 0x00df d2ddatalo r data[7:0] w table 65. 0x00e0?0x0e7 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e0- 0x00e7 reserved r00000000 w table 66. 0x00e8?0x00ef serial peripheral interface (spi) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e8 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00e9 spicr2 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w 0x00ea spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00eb spisr r spif 0 sptef modf 0 0 0 0 w 0x00ec spidrh r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 0x00ed spidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 0x00ee reserved r00000000 w 0x00ef reserved r00000000 w table 67. 0x00f0?0x0ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e0- 0x00ff reserved r00000000 w table 64. 0x00d8?0x00df die 2 die initiator (d2di) map 1 of 3
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 46 table 68. 0x0100?0x011f flash module (ftmrc) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0100 fclkdiv rfdivld fdivlck fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0102 fccobix r00000 ccobix2 ccobix1 ccobix0 w 0x0103 reserved r00000000 w 0x0104 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0105 fercnfg r000000 dfdie sfdie w 0x0106 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0107 ferstat r000000 dfdif sfdif w 0x0108 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0109 dfprot r dpopen 000 dps3 dps2 dps1 dps0 w 0x010a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x010b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x010c reserved r00000000 w 0x010d reserved r00000000 w 0x010e reserved r00000000 w 0x010f reserved r00000000 w 0x0110 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0111 reserved r00000000 w 0x0112 reserved r00000000 w 0x0113 reserved r00000000 w
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 47 table 69. 0x0120 port integration module (pim) map 3 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0120 ptia r ptia7 ptia6 ptia5 ptia4 ptia3 ptia2 ptia1 ptia0 w 0x0121 ptib r000000ptib1ptib0 w 0x0122- 0x017f reserved r00000000 w table 70. 0x0180?0x1ef reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0180- 0x01ef reserved r00000000 w table 71. 0x01f0?0x01ff clock and power management (cpmu) map 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01f0 reserved r00000000 w 0x01f1 cpmu lvctl r00 000lvds lvie lvif w 0x01f6 reserved r00000000 w 0x01f7 reserved r00000000 w 0x01f8 cpmu irctrimh r tctrim[3:0] 00 irctrim[9:8] w 0x01f9 cpmu irctriml r irctrim[7:0] w 0x01fa cpmuosc r osce oscbw oscpins_ en oscfilt[4:0] w 0x01fb cpmuprot r0000000 prot w 0x01fc reserved r00000000 w table 72. 0x01fd?0x1ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01fd- 0x01ff reserved r00000000 w table 73. 0x0200?0x03ff die-to-die initiator blocking and non-blocking access window address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 48 table 74 shows the detailed module maps of the mm912_634 analog die. 0x0200- 0x02ff blocking access window r w 0x0300- 0x03ff non-blocking access window r w table 74. analog die registers (57) - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset name 76543210 0x00 isr (hi) r 0 0 hot lsot hsot linot sci rx interrupt source register w 0x01 isr (lo) r tx err tov ch3 ch2 ch1 ch0 vsi interrupt source register w 0x02 ivr r 0 0 irq interrupt vector register w 0x04 vcr r 0 0 0 vrovie htie hvie lvie lbie voltage control register w 0x05 vsr r 0 0 0 vrovc htc hvc lvc lbc voltage status register w 0x08 lxr r 0 0 l5 l4 l3 l2 l1 l0 lx status register w 0x09 lxcr r 0 0 l5ds l4ds l3ds l2ds l1ds l0ds lx control register w 0x10 wdr r wdoff wdwo 0 0 0 wdto watchdog register w 0x11 wdsr r wdsr watchdog service register w 0x12 wcr r cssel l5we l4we l3we l2we l1we l0we wake up control register w 0x13 tcr r fwm cst timing control register w 0x14 wsr r fwu linwu l5wu l4wu l3wu l2wu l1wu l0wu wake up source register w 0x15 rsr r 0 0 wdr exr wur lvrx lvr por reset status register w 0x16 mcr r000000 mode mode control register w 0x18 linr r linotie linotc rx tx lvsd linen linsr lin register w 0x20 ptbc1 r 0 pueb2 pueb1 pueb0 0 ddrb2 ddrb1 ddrb0 port b configuration register 1 w 0x21 ptbc2 r 0 0 0 0 pwmcs pwmen sermod port b config register 2 w table 73. 0x0200?0x03ff die-to-die initiator blocking and non-blocking access window
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 49 0x22 ptb r00000 ptb2 ptb1 ptb0 port b data register w 0x28 hscr r hsotie hshvsd e pwmcs2 pwmcs1 pwmhs2 pwmhs1 hs2 hs1 high side control register w 0x29 hssr r hsotc 0 0 0 hs2cl hs1cl hs2ol hs1ol high side status register w 0x30 lscr r lsotie 0 pwmcs2 pwmcs1 pwmls2 pwmls1 ls2 ls1 low side control register w 0x31 lssr r lsotc 0 0 0 ls2cl ls1cl ls2ol ls1ol low side status register w 0x32 lscen r0000 lscen low-side control enable register w 0x38 hsr r hotie hotc00000 hsupon hall supply register w 0x3c csr r cse 000 ccd csgs current sense register w 0x40 scibd (hi) r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 sci baud rate register w 0x41 scibd (lo) r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 sci baud rate register w 0x42 scic1 r loops 0 rsrc m 0 ilt pe pt sci control register 1 w 0x43 scic2 r tie tcie rie ilie te re rwu sbk sci control register 2 w 0x44 scis1 r tdre tc rdrf idle or nf fe pf sci status register 1 w 0x45 scis2 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf sci status register 2 w 0x46 scic3 r r8 t8 txdir txinv orie neie feie peie sci control register 3 w 0x47 scid rr7r6r5r4r3r2r1r0 sci data register wt7t6t5t4t3t2t1t0 0x60 pwmctl r cae1 cae0 pclk1 pclk0 ppol1 ppol0 pwme1 pwme0 pwm control register w 0x61 pwmprclk r 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 pwm presc. clk select reg w 0x62 pwmscla r bit 7 6 5 4 3 2 1 bit 0 pwm scale a register w 0x63 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 pwm scale b register w table 74. analog die registers (57) - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset name 76543210
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 50 0x64 pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 pwm ch counter reg 0 w 0 0 0 0 0 0 0 0 0x65 pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 pwm ch counter reg 1 w 0 0 0 0 0 0 0 0 0x66 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 pwm ch period register 0 w 0x67 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 pwm ch period register 1 w 0x68 pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 pwm ch duty register 0 w 0x69 pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 pwm ch duty register 1 w 0x80 acr r scie cce oce adcrst 0 ps2 ps1 ps0 adc config register w 0x81 asr r scf 2p5clf 0 0 ccnt3 ccnt2 ccnt1 ccnt0 adc status register w 0x82 accr (hi) r ch15 ch14 0 ch12 ch11 ch10 ch9 ch8 adc conversion ctrl reg w 0x83 accr (lo) r ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 adc conversion ctrl reg w 0x84 accsr (hi) r cc15 cc14 0 cc12 cc11 cc10 cc9 cc8 adc conv complete reg w 0x85 accsr (lo) r cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 adc conv complete reg w 0x86 adr0 (hi) r adr0 9 adr0 8 adr0 7 adr0 6 adr0 5 adr0 4 adr0 3 adr0 2 adc data result register 0 w 0x87 adr0 (lo) r adr0 1 adr0 0 0 0 0 0 0 0 adc data result register 0 w 0x88 adr1 (hi) r adr1 9 adr1 8 adr1 7 adr1 6 adr1 5 adr1 4 adr1 3 adr1 2 adc data result register 1 w 0x89 adr1 (lo) r adr1 1 adr1 0 0 0 0 0 0 0 adc data result register 1 w 0x8a adr2 (hi) r adr2 9 adr2 8 adr2 7 adr2 6 adr2 5 adr2 4 adr2 3 adr2 2 adc data result register 2 w 0x8b adr2 (lo) r adr2 1 adr2 0 0 0 0 0 0 0 adc data result register 2 w 0x8c adr3 (hi) r adr3 9 adr3 8 adr3 7 adr3 6 adr3 5 adr3 4 adr3 3 adr3 2 adc data result register 3 w 0x8d adr3 (lo) r adr3 1 adr3 0 0 0 0 0 0 0 adc data result register 3 w 0x8e adr4 (hi) r adr4 9 adr4 8 adr4 7 adr4 6 adr4 5 adr4 4 adr4 3 adr4 2 adc data result register 4 w table 74. analog die registers (57) - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset name 76543210
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 51 0x8f adr4 (lo) r adr4 1 adr4 0 0 0 0 0 0 0 adc data result register 4 w 0x90 adr5 (hi) r adr5 9 adr5 8 adr5 7 adr5 6 adr5 5 adr5 4 adr5 3 adr5 2 adc data result register 5 w 0x91 adr5 (lo) r adr5 1 adr5 0 0 0 0 0 0 0 adc data result register 5 w 0x92 adr6 (hi) r adr6 9 adr6 8 adr6 7 adr6 6 adr6 5 adr6 4 adr6 3 adr6 2 adc data result register 6 w 0x93 adr6 (lo) r adr6 1 adr6 0 0 0 0 0 0 0 adc data result register 6 w 0x94 adr7 (hi) r adr7 9 adr7 8 adr7 7 adr7 6 adr7 5 adr7 4 adr7 3 adr7 2 adc data result register 7 w 0x95 adr7 (lo) r adr7 1 adr7 0 0 0 0 0 0 0 adc data result register 7 w 0x96 adr8 (hi) r adr8 9 adr8 8 adr8 7 adr8 6 adr8 5 adr8 4 adr8 3 adr8 2 adc data result register 8 w 0x97 adr8 (lo) r adr8 1 adr8 0 0 0 0 0 0 0 adc data result register 8 w 0x98 adr9 (hi) r adr9 9 adr9 8 adr9 7 adr9 6 adr9 5 adr9 4 adr9 3 adr9 2 adc data result register 9 w 0x99 adr9 (lo) r adr9 1 adr9 0 0 0 0 0 0 0 adc data result register 9 w 0x9a adr10 (hi) r adr10 9 adr10 8 adr10 7 adr10 6 adr10 5 adr10 4 adr10 3 adr10 2 adc data result reg 10 w 0x9b adr10 (lo) r adr10 1 adr10 0 0 0 0 0 0 0 adc data result reg 10 w 0x9c adr11 (hi) r adr11 9 adr11 8 adr11 7 adr11 6 adr11 5 adr11 4 adr11 3 adr11 2 adc data result reg 11 w 0x9d adr11 (lo) r adr11 1 adr11 0 0 0 0 0 0 0 adc data result reg 11 w 0x9e adr12 (hi) r adr12 9 adr12 8 adr12 7 adr12 6 adr12 5 adr12 4 adr12 3 adr12 2 adc data result reg 12 w 0x9f adr12 (lo) r adr12 1 adr12 0 0 0 0 0 0 0 adc data result reg 12 w 0xa2 adr14 (hi) r adr14 9 adr14 8 adr14 7 adr14 6 adr14 5 adr14 4 adr14 3 adr14 2 adc data result reg 14 w 0xa3 adr14 (lo) r adr14 1 adr14 0 0 0 0 0 0 0 adc data result reg 14 w 0xa4 adr15 (hi) r adr15 9 adr15 8 adr15 7 adr15 6 adr15 5 adr15 4 adr15 3 adr15 2 adc data result reg 15 w 0xa5 adr15 (lo) r adr15 1 adr15 0 0 0 0 0 0 0 adc data result reg 15 w table 74. analog die registers (57) - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset name 76543210
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 52 0xc0 tios r 0 0 0 0 ios3 ios2 ios1 ios0 tim incap/outcomp select w 0xc1 cforc r00000000 timer compare force reg w foc3 foc2 foc1 foc0 0xc2 oc3m r 0 0 0 0 oc3m3 oc3m2 oc3m1 oc3m0 output comp 3 mask reg w 0xc3 oc3d r 0 0 0 0 oc3d3 oc3d2 oc3d1 oc3d0 output comp 3 data reg w 0xc4 tcnt (hi) r tcnt 15 tcnt 14 tcnt 13 tcnt 12 tcnt 11 tcnt 10 tcnt 9 tcnt 8 timer count register w 0xc5 tcnt (lo) r tcnt 7 tcnt 6 tcnt 5 tcnt 4 tcnt 3 tcnt 2 tcnt 1 tcnt 0 timer count register w 0xc6 tscr1 r ten 00 tffca 0000 timer system control reg 1 w 0xc7 ttov r 0 0 0 0 tov3 tov2 tov1 tov0 timer toggle overflow reg w 0xc8 tctl1 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 timer control register 1 w 0xc9 tctl2 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a timer control register 2 w 0xca tie r0000 c3i c2i c1i c0i timer interrupt enable reg w 0xcb tscr2 r toi 000 tcre pr2 pr1 pr0 timer system control reg 2 w 0xcc tflg1 r0000 c3f c2f c1f c0f main timer interrupt flag 1 w 0xcd tflg2 r tof 0000000 main timer interrupt flag 2 w 0xce tc0 (hi) r tc0 15 tc0 14 tc0 13 tc0 12 tc0 11 tc0 10 tc0 9 tc0 8 tim incap/outcomp reg 0 w 0xcf tc0 (lo) r tc0 7 tc0 6 tc0 5 tc0 4 tc0 3 tc0 2 tc0 1 tc0 0 tim incap/outcomp reg 0 w 0xd0 tc1 (hi) r tc1 15 tc1 14 tc1 13 tc1 12 tc1 11 tc1 10 tc1 9 tc1 8 tim incap/outcomp reg 1 w 0xd1 tc1 (lo) r tc1 7 tc1 6 tc1 5 tc1 4 tc1 3 tc1 2 tc1 1 tc1 0 tim incap/outcomp reg 1 w 0xd2 tc2 (hi) r tc2 15 tc2 14 tc2 13 tc2 12 tc2 11 tc2 10 tc2 9 tc2 8 tim incap/outcomp reg 2 w 0xd3 tc2 (lo) r tc2 7 tc2 6 tc2 5 tc2 4 tc2 3 tc2 2 tc2 1 tc2 0 tim incap/outcomp reg 2 w 0xd4 tc3 (hi) r tc3 15 tc3 14 tc3 13 tc3 12 tc3 11 tc3 10 tc3 9 tc3 8 tim incap/outcomp reg 3 w table 74. analog die registers (57) - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset name 76543210
functional description and application information mm912_634 advance information, rev. 4.0 freescale semiconductor 53 0xd5 tc3 (lo) r tc3 7 tc3 6 tc3 5 tc3 4 tc3 3 tc3 2 tc3 1 tc3 0 tim incap/outcomp reg 3 w 0xf0 ctr0 r lintre lintr wdctre ctr0_4 ctr0_3 wdctr2 wdctr1 wdctr0 trimming reg 0 w 0xf1 ctr1 r bgtre ctr1_6 bgtrim up bgtrim dn ireftre ireftr2 ireftr1 ireftr0 trimming reg 1 w 0xf2 ctr2 r ctr2_e ctr2_1 ctr2_0 slpbgt re slpbg_l ock slpbgt r2 slpbgt r1 slpbgt r0 trimming reg 2 w 0xf3 ctr3 r offctr e offctr 2 offctr 1 offctr 0 ctr3_e ctr3_2 ctr3_1 ctr3_0 trimming reg 3 w 0xf4 srr r0000 fmrev mmrev silicon revision register w note: 57. registers not shown are reserved and must not be accessed. table 74. analog die registers (57) - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset name 76543210
mm912_634 - analog die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 54 4.3 mm912_634 - analog die overview 4.3.1 introduction the mm912_634 anal og die implements all system ba se functionality to operate th e integrated microcontroller, and delivers application spec ific actuator control as well as input capturing. 4.3.2 system registers 4.3.2.1 silicon revision register (srr) note please refer to the mm912f634er - mask set errata document for details on the analog die mask revisions. 4.3.3 analog die options the following section describes the differ ences between analog die options 1 and 2. note this document will describe the features and f unctions of option 1 (all modules available and tested). beyond this chapter, there will be no ad ditional note or differentiation between the different implementations. 4.3.3.1 current sense module for device options with the current sense module not available, the following considerations are to be made. table 75. silicon revision register (srr) offset (58) 0xf4 access: user read 76543210 r 0 0 0 0 fmrev mmrev w note: 58. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 76. srr - register field descriptions field description 3-2 fmrev mm912_634 analog die silicon revision register full mask revision - the three bits represent the revision count of full mask change. read only, writing will have no effec t. the first full mask will have the count 00. 1-0 mmrev mm912_634 analog die silicon revision register metal tweak revision - the three bits represent the count of metal tweaks applied to the full mask.read only, writing will hav e no effect. the first full mask will have the count 00. table 77. analog die options feature option 1 option 2 current sense module yes no wake up inputs (lx) l0?l5 l0.l3 analog mcu
mm912_634 advance information, rev. 4.0 freescale semiconductor 55 4.3.3.1.1 pinout considerations 4.3.3.1.2 register considerations the current sense register must remain in default (0x00) state. the conversion control register - bit 9 must always be written 0. the conversion complete register - bit 9 must be ignored. the adc data result reg 9 must be ignored. 4.3.3.1.3 functional considerations ? the complete current sense module is not available. ? the adc channel 9 is not available. 4.3.3.2 wake-up inputs (lx) for device options with reduced number of wake up i nputs (lx), the following considerations are to be made. 4.3.3.2.1 pinout considerations 4.3.3.2.2 register considerations the lx - bit for the not available lx input in the lx status register must be ignored. table 78. isense - pin considerations pin pin name for option 1 new pin name comment 40 isensel nc isense feature not bonded and/or not tested. connect pins 40 and 41 (nc) to gnd. 41 isenseh nc offset name 76543210 0x3c csr r cse 000 ccd csgs current sense register w 0x82 accr (hi) r ch15 ch14 0 ch12 ch11 ch10 ch9 ch8 adc conversion ctrl reg w 0x84 accsr (hi) r cc15 cc14 0 cc12 cc11 cc10 cc9 cc8 adc conv complete reg w 0x98 adr9 (hi) r adr9 9 adr9 8 adr9 7 adr9 6 adr9 5 adr9 4 adr9 3 adr9 2 adc data result register 9 w 0x99 adr9 (lo) r adr9 1 adr9 0 0 0 0 0 0 0 adc data result register 9 w table 79. lx - pin considerations pin pin name for option 1 new pin name comment 31?36 lx nc one or more lx wake up inputs are not availabl e based on the analog die option. not available lx inputs are not bonded and/or not tested. connect not available lx pins (nc) to gnd. rlx is not required on those pins.
mm912_634 advance information, rev. 4.0 freescale semiconductor 56 the lx control register for the not av ailable lx input must be written 0. a not available lx input can not be selected as wake-up source and must have its lxwe bit set to 0. the wake-up source register for not available lx inputs must be ignored. the conversion control register fo r the not available lx analog input (3?8) must always be written 0. the conversion complete register for the not av ailable lx analog input (3.8) must be ignored. the adc data result register for the not av ailable lx analog input (3.8) must be ignored. 4.3.3.2.3 functional considerations for the not available lx inputs, the following functions are limited: ? no wake-up feature / cyclic sense ? no digital input ? no analog input and conversion via adc offset name 76543210 0x08 lxr r 0 0 l5 l4 l3 l2 l1 l0 lx status register w 0x09 lxcr r 0 0 l5ds l4ds l3ds l2ds l1ds l0ds lx control register w 0x12 wcr r cssel l5we l4we l3we l2we l1we l0we wake up control register w 0x14 wsr r fwu linwu l5wu l4wu l3wu l2wu l1wu l0wu wake up source register w 0x82 accr (hi) r ch15 ch14 0 ch12 ch11 ch10 ch9 ch8 adc conversion ctrl reg w 0x83 accr (lo) r ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 adc conversion ctrl reg w 0x84 accsr (hi) r cc15 cc14 0 cc12 cc11 cc10 cc9 cc8 adc conv complete reg w 0x85 accsr (lo) r cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 adc conv complete reg w 0x8c-0 x97 adrx (hi) r adrx 9 adrx 8 adrx 7 adrx 6 adrx 5 adrx 4 adrx 3 adrx 2 adc data result register x w adrx (lo) r adrx 1 adrx 0 0 0 0 0 0 0 adc data result register x w
modes of operation mm912_634 advance information, rev. 4.0 freescale semiconductor 57 4.4 modes of operation the mm912_634 analog die offers three main operating modes: normal (run), stop, and sleep. in normal mode, the device is active and is operating under normal appl ication conditions. in stop mode, the voltage regulator operates with limited current capability, the external load is expected to be reduced while in stop mode. in sleep mode both voltage regulators are turned off (v dd =v ddx =0v). wake-up from stop mode is indicated by an interrupt signal . wake-up from sleep mode will change the mm912_634 analog die into reset mode while the voltage regulator is turned back on. the selection of the different modes is c ontrolled by the mode control register (mcr). figure 16 describes how transitions are done be tween the different operating modes. figure 16. modes of operation and transitions 4.4.1 power down mode for the device power (vs1) below v por , the mm912_634 analog die is virtually in power down mode. once vs1>vpor, the mm912_634 analog die will enter reset mode with the condition ?power on reset - por?. 4.4.2 reset mode the mm912_634 analog die enters reset mode if a reset condition occurs (por - power on reset, lvr- low voltage reset, low voltage vddx reset - lvrx, wdr - watchdog reset, exr - external reset, and wur - wake-up sleep reset). for internal reset sources, the reset_a pin is driven low for trst after the reset condition is gone. after this delay, the reset_a pin is released. with a high detected on the reset_a pin, vdd>vlvr and vddx>vlvrx the mm912_634 analog die enters in normal mode. to avoid short-circuit conditions being present for a long time, a tvto timeout is implemented. once vdd < vlvr or vddx < vlvrx with vs1 > (vlvi + vlvi_h) for more than tvto, the mm 912_634 analog die will transit directly to sleep mode. analog mcu power down reset normal mode stop mode sleep mode power up (por = 1) v dd high and reset delay (t rst ) expired wake up wake up external or internal reset power down (v sup modes of operation mm912_634 advance information, rev. 4.0 freescale semiconductor 58 the reset status register (rsr) will indicate the source of the reset by individual flags. ? por - power on reset ? lvr - low voltage reset vdd ? lvrx - low voltage reset vddx ? wdr - watchdog reset ? exr - external reset ? wur - wake-up sleep reset see also section 4.8, ?resets . 4.4.3 normal mode in normal mode, all mm912_634 analog die user functions are active and can be controlled by the d2d interface. both regulators (vdd and vddx) are active and oper ate with full current capability. once entered in normal mode, the watchdog will operate as a si mple non-window watchdog with an initial timeout (tiwdto) to be reset via the d2d interface. after the initial rese t, the watchdog will operate in standard window mode. see section 4.10, ?window watchdog for details. 4.4.4 stop mode the stop mode will allow reduced current cons umption with fast startup time. in this mode, both voltage regulators (vdd and vddx) are active, with limited current drive capability. in this condition, the mcu is suppose d to operate in low power mode (stop). note to avoid any pending analog die interrupt s prevent the mcu from entering mcu stop resulting in unexpected system behavior, the analog die irq sources should be disabled and the corresponding flags be cleared before entering stop. the device can enter in stop mode by configuring the mode cont rol register (mcr) via the d2d interface. the mcu has to enter a low power mode immediately afterwards executing the stop in struction. the wake-up source register (wsr) has to be read after a wake-up condition in order to execute a new stop mode command. two base clock cycles (fbase) delay are required between wsr read and mcr write. while in stop mode, the mm912_634 analog die will wake up on the following sources: ? lx - wake-up (maskable with selectable cyclic sense) ? forced wake-up (configurable timeout) ? lin wake-up ? d2d wake-up (special command) after wake-up from the sources listed abov e, the device will transit to normal mode. reset will wake up the device directly to reset mode. see section 4.9, ?wake-up / cyclic sense for details. 4.4.5 sleep mode the sleep mode will allow very low current consumption. in this mode, both voltage regulators (vdd and vddx) are inactive. the device can enter into sleep mode by configuring the mode control register (mcr) via the d2d- interface. during sleep mode, all unused internal blocks are deactivated to allow th e lowest possible consumption. power consumption will decrease further if the cyclic sense or forced wa ke-up feature are disabled. while in sleep mode, the mm912_634 analog die will wake up on the following sources: ? lx - wake-up (maskable with selectable cyclic sense) ? forced wake-up (configurable timeout) ? lin wake-up after wake-up from the sources listed above or a reset condition, the device will transit to reset mode. see section 4.9, ?wake-up / cyclic sense for details.
modes of operation mm912_634 advance information, rev. 4.0 freescale semiconductor 59 4.4.6 analog die functionality by operation mode 4.4.7 register definition 4.4.7.1 mode control register (mcr) table 80. operation mode overview function reset normal stop sleep vdd/vddx full full stop off hsup off full off off lsx full off off hsx full cyclic sense (59) cyclic sense (59) adc full off off d2d full functional off lx full wake-up (59) wake-up (59) ptbx full off off lin full wake-up (59) wake-up (59) watchdog full (60) off off vsense full off off csense full off off cyclic sense not ac tive cyclic sense (59) cyclic sense (59) note: 59. if configured. 60. special init through non window watchdog. table 81. mode control register (mcr) offset (61) 0x16 access: user read/write 76543210 r 0 0 0 000 mode w reset00000000 note: 61. offset related to 0x0200 for blocking access and 0x3 00 for non blocking access wi thin the global address space. table 82. mcr - register field descriptions field description 1-0 mode mode select - these bits will issue a trans ition from to the selected operating mode. 00 - normal mode. only with effect in stop mode. will issue wake up and transition to normal mode. 01 - stop mode. will initiate transition to stop mode. (62) 10 - sleep mode. will initiate transition to sleep mode. 11 - normal mode. note: 62. the wake-up source register (wsr) has to be read after a wake-up condition in order to execute a new stop mode command. two base clock cycles (fbase) delay are re quired between wsr read and mcr write.
power supply mm912_634 advance information, rev. 4.0 freescale semiconductor 60 4.5 power supply the mm912_634 analog die supplies vdd (2.5 v), vddx (5.0 v), and hsup, based on the supply voltage applied to the vs1 pin. vdd is cascaded of t he vddx regulator. to separate the high side outputs from the main power supply, the vs2 pin does only power the high side driv ers. both supply pins have to be externally protected against reverse battery conditions. to supply external hall effect sensors, the hsup pin will supply a switchable regulated supply. see section 4.11, ?hall sensor supply output - hsup . a reverse battery protected input (vsense) is implemented to measure the battery voltage directly. a serial resistor ( r vsense) is required on this pin. see section 4.23, ?supply voltage sense - vsense . in addition, the vs1 supply can be routed to the adc (vs1sense) to measure the vs1 pin voltage directly. see section 4.24, ?internal supply voltage sense - vs1sense . to have an independent adc verification, the internal sle ep mode bandgap voltage can be routed to the adc (bandgap). as this node is independent from the adc reference, any out of range result would indicate malfunctioning adc or bandgap reference. see section 4.25, ?internal bandgap reference voltage sense - bandgap . to stabilize the internal adc reference voltage for higher prec ision measurements, the current limited adc2p5 pin needs to be connected to an external filter capacitor ( c adc2p5). it is not recommended to connect additional loads to this pin. see section 4.20, ?analog digital converter - adc . the following safety f eatures are implemented: ? lbi - low battery interrupt, internally measured at vsense ? lvi - low voltage interrupt, internally measured at vs1 ? hvi - high voltage interrupt, internally measured at vs2 ? vrovi - voltage regulator over-voltage interrupt internally measured at vdd and vddx ? lvr - low voltage reset, internally measured at vdd ? lvrx - low voltage reset, internally measured at vddx ? hti - high temperature interrupt measured between the vdd and vddx regulators ? over-temperature shutdown measured between the vdd and vddx regulators figure 17. mm912_634 power supply analog mcu vddx (5v) regulator vdd (2.5v) regulator hsup (18v) regulator hs1 & hs2 adc vs2 vs1 vsense hsup hs1 hs2 vddx vdd adc 2.5v reference vddx internal vdd internal adc2p5 c vddx c vdd c adc c hsup hvi lvi lbi lvr lvrx vrov bg1p25sleep
power supply mm912_634 advance information, rev. 4.0 freescale semiconductor 61 4.5.1 voltage regulators vdd (2.5 v) & vddx (5.0 v) to supply the mcu die and minor additional loads two cascaded voltage regulators have been implemented, vddx (5.0 v) and vdd (2.5 v). external capacitors (cvdd) and (cvddx) are required for proper regulation. 4.5.2 power up behavior / power down behavior - i64 to guarantee safe power up and down behavior, special depend encies are implemented to prev ent unwanted mcu execution. figure 18 shows a standard power up and power down sequence. figure 18. power up / down sequence to avoid any critical behavior, it is essential to have t he mcu power on reset (por) active when the analog die reset (reset_a ) is not fully active. as the reset_a circuity is supplied by vddx, vdd needs to be below the por threshold when vddx is to low to guarantee reset_a active (3;6). this is achiev ed with the following implementation. power up: ? the vdd regulator is enabled after vddx has reached the v lvrx threshold (1). ? once vdd reaches v lrv , the reset_a is released (2). ? the mcu is also protected by the mcu_lvr. power down: ? once vddx has reached the v lvrx threshold (4), the vdd regulator is disa bled and the regulator output is actively pulled down to discharge any vdd capacitance (5). reset_a is activated as well. ? the active discharge guarantees vdd to be below por level before vddx discharges below critical level for the reset circuity. note the behavior explained previously is essentia l for the mc9s12i64 mcu die used, as this mcu does have an internal regulator stage, but the lvr function only active in normal modemc9s12i64. the shutdown behavior should be considered when sizing the external capacitors c vdd and c vddx for extended low voltage operation. mcu_por 5v v lbi / v lvi normal operating range (not to scale) v lvrx v lvr v por_a reset_a vddx vdd vsup v por_mcu v rovx v rox 1 4 5 6 2 3 / v lvr_mcu mcu_lvr mcu_lvr mcu_por
power supply mm912_634 advance information, rev. 4.0 freescale semiconductor 62 4.5.3 register definition 4.5.3.1 voltage control register (vcr) 4.5.3.2 voltage status register (vsr) table 83. voltage control register (vcr) offset (63) 0x04 access: user read/write 76543210 r 0 0 0 vrovie htie hvie lvie lbie w reset00000000 note: 63. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 84. vcr - register field descriptions field description 4 vrovie voltage regulator over-voltage interrupt enable ? enables the interrupt for the regulator over-voltage condition. 0 - voltage regulator over-voltage interrupt is disabled 1 - voltage regulator over-voltage interrupt is enabled 3 htie high temperature interrupt enable ? enables the interrupt for the voltage regulator (vdd/vddx) temperature warning. 0 - high temperature interrupt is disabled 1 - high temperature interrupt is enabled 2 hvie high voltage interrupt enable ? enables the interrupt for the vs2 - high voltage warning. 0 - high voltage interrupt is disabled 1 - high voltage interrupt is enabled 1 lvie low voltage interrupt enable ? enables the interrupt for the vs1 - low voltage warning. 0 - low voltage interrupt is disabled 1 - low voltage interrupt is enabled 0 lbie low battery interrupt enable ? enables the interrupt for the vsense - low battery voltage warning. 0 - low battery interrupt is disabled 1 - low battery interrupt is enabled table 85. voltage status register (vsr) offset (64) 0x05 access: user read 76543210 r 0 0 0 vrovc htc hvc lvc lbc w reset00000000 note: 64. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space.
power supply mm912_634 advance information, rev. 4.0 freescale semiconductor 63 table 86. vsr - register field descriptions field description 4 vrovc voltage regulator over-voltage condition - th is status bit indicates an over-voltage wa rning is present for at least one of the main voltage regulators (vdd or vddx). reading the r egister will clear the vrovi flag if present. see section 4.7, ?interrupts for details. note: this feature requires the trimming of section 4.26.1.2.3, ?trimming register 2 (ctr2) to be done to be effective. untrimmed devices may issue the vrovc c ondition including the ls turn off at normal operation! 0 - no voltage regulator over-voltage condition present. 1 - voltage regulator over-voltage condition present. 3 htc high temperature condition - this status bit indicates a hi gh temperature warning is present for the voltage regulators (vdd/vddx). reading the register will clear the hti flag if present. see section 4.7, ?interrupts for details. 0 - no high temperature condition present. 1 - high temperature condition present. 2 hvc high voltage condition - this status bit indicates a high voltage wa rning for vs2 is present. readi ng the register will clear t he hvi flag if present. see section 4.7, ?interrupts for details. 0 - no high voltage condition present. 1 - high voltage condition present. 1 lvc low voltage condition - this status bit indicates a low voltage warning for vs1 is present. reading the register will clear the lvi flag if present. see section 4.7, ?interrupts for details. 0 - no low voltage condition present. 1 - low voltage condition present. 0 lbc low battery condition - this status bit indicates a low voltage warning for vsense is present. reading the register will clear the lbi flag if present. see section 4.7, ?interrupts for details. 0 - no low battery condition present. 1 - low battery condition present.
die to die interface - target mm912_634 advance information, rev. 4.0 freescale semiconductor 64 4.6 die to die interface - target the d2d interface is the bus interface to the microcontr oller. access to the mm912_634 analog die is controlled by the d2d interface module. this section describes t he functionality of the die-to-die target block (d2d). 4.6.1 overview the d2d is the target for a data transfer from the target to t he initiator (mcu). the initiator provides a set of configuration registers and two memory mapped 256 byte address windows. when writi ng to a window, a transaction is initiated sending a write command, followed by an 8-bit address, and the data byte or word is received from the initiator. when reading from a window, a transaction is received with the read command, followed by an 8-bit address. the target then responds with the data. the basic idea is that a peripheral located on the mm912_634 anal og die, can be addressed like an on-chip peripheral. features: ? software transparent register access to peripherals on the mm912_634 analog die ? 256 byte address window ? supports blocking read or write, as well as non-blocking write transactions ? 4-bit physical bus width ? automatic synchronization of the target when initiator starts driving the interface clock ? generates transaction and error status as well as eot acknowledge ? providing single interrupt interface to d2d initiator 4.6.2 low power mode operation the d2d module is disabled in sleep mode. in stop mode, the d2 dint signal is used to wake-up a powered down mcu. as the mcu could wake-up without the mm912_634 analog die, a s pecial command will be recognized as a wake-up event during stop mode. see section 4.4, ?modes of operation . 4.6.2.1 normal mode / stop mode while in normal or stop mode, d2dclk acts as input only with pu ll present. d2d[3:0] operates as an inpu t/output with pull-down always present. d2dint acts as output only. note the maximum allowed clock speed of the interface is limited to f d2d . 4.6.2.2 sleep mode while in sleep mode, all interface data pins are pulled down to dgnd to reduce power consumption. analog mcu
interrupts mm912_634 advance information, rev. 4.0 freescale semiconductor 65 4.7 interrupts interrupts are used to signal a microcontroller that a peripheral needs to be serviced. while in stop mode, the interrupt signal is used to signal wake-up events. the interrupts are signaled by an active high level of the d2dint pin, which will remain high until the interrupt is ackno wledged via the d2d-interface. interrupts are only asserted while in normal mode. 4.7.1 interrupt source identification once an interrupt is signalized, there are tw o options to identify the corresponding source(s). 4.7.1.1 interrupt source mirror all interrupt sources in mm912_634 analog die are mirrored to a spec ial interrupt source register (isr). this register is read only and will indicate all currently pending interrupts. reading th is register will not acknowledge any interrupt. an additiona l d2d access is necessary to serve the specific module. note the vsi - voltage status interrupt combines the five status flags for the low battery interrupt, low voltage interrupt, high volt age interrupt, voltage regulator over-voltage interrupt, and the voltage regulator high temperature interrupt. the specific source can be identified by reading the voltage status register - vsr. 4.7.1.1.1 interrupt source register (isr) table 87. interrupt source register (isr) offset (65) 0x00 (0x00 and 0x01 for 8bit access) access: user read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 hot lsot hsot linot sci rx tx err tov ch3 ch2 ch1 ch0 vsi w note: 65. offset related to 0x0200 for blocking access and 0x300 for non blocking access wi thin the global address space. table 88. isr - regist er field descriptions field description 0 - vsi vsi - voltage status interrupt combining the following sources: ? low battery interrupt ? low voltage interrupt ? high voltage interrupt ? voltage regulator over-voltage interrupt ? voltage regulator high temperature interrupt 1 - ch0 ch0 - tim channel 0 interrupt 2 - ch1 ch1 - tim channel 1 interrupt 3 - ch2 ch2 - tim channel 2 interrupt 4 - ch3 ch3 - tim channel 3 interrupt 5 - tov tov - timer overflow interrupt 6 - err err - sci error interrupt 7 - tx tx - sci transmit interrupt 8 - rx rx - sci receive interrupt 9 - sci sci - adc sequence complete interrupt 10 - linot linot - lin driver over-temperature interrupt 11 - hsot hsot - high side over-temperature interrupt 12 - lsot lsot - low side over-temperature interrupt 13 - hot hot - hsup over-temperature interrupt analog mcu
interrupts mm912_634 advance information, rev. 4.0 freescale semiconductor 66 4.7.1.2 interrupt vector emulation by priority to allow a vector based interrupt handling by the mcu, the number of the highest prioritized interrupt pending is returned in t he interrupt vector register. to allow an offset based vector table, the result is pre-shifted (mult iple of 2). reading this regis ter will not acknowledge an interrupt. an additional d2d ac cess is necessary to serve the specific module. 4.7.1.2.1 interrupt vector register (ivr) the following table is listing all mm912_634 analog die interrupt sources with the corresponding priority. 4.7.2 interrupt sources 4.7.2.1 voltage status interrupt (vsi) the voltage status interrupt - vsi combines the five interrupt sources of the voltage status register. it is only available in the interrupt source register (isr). ackno wledge the interrupt by reading the voltage status register - vsr. to issue a new table 89. interrupt vector register (ivr) offset (66) 0x02 access: user read 76543210 r 0 0 irq w note: 66. offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 90. ivr - regist er field descriptions field description 5:0 irq represents the highest prioritized interrupt pending. see table 91 in case no interrupt is pending, the result will be 0. table 91. interrupt source priority interrupt source irq priority no interrupt pending or wake-up from stop mode 0x00 1 (highest) lvi - low voltage interrupt 0x02 2 hti - voltage regulator high temperature interrupt 0x04 3 lbi - low battery interrupt 0x06 4 ch0 - tim channel 0 interrupt 0x08 5 ch1 - tim channel 1 interrupt 0x0a 6 ch2 - tim channel 2 interrupt 0x0c 7 ch3 - tim channel 3 interrupt 0x0e 8 tov - timer overflow interrupt 0x10 9 err - sci error interrupt 0x12 10 tx - sci transmit interrupt 0x14 11 rx - sci receive interrupt 0x16 12 sci - adc sequence complete interrupt 0x18 13 linot - lin driver over-temperature interrupt 0x1a 14 hsot - high side over-temperature interrupt 0x1c 15 lsot - low side over-temperature interrupt 0x1e 16 hot - hsup over-temperature interrupt 0x20 17 hvi - high voltage interrupt 0x22 18 vrovi - voltage regulator over-voltage interrupt 0x24 19 (lowest)
interrupts mm912_634 advance information, rev. 4.0 freescale semiconductor 67 interrupt, the condition has to vanish and occur again. see section 4.5, ?power supply for details on the voltage status register including masking information. 4.7.2.2 low voltage interrupt (lvi) acknowledge the interrupt by reading the vo ltage status register - vsr. to issue a new interrupt, the condition has to vanish and occur again. see section 4.5, ?power supply for details on the voltage status register including masking information. 4.7.2.3 voltage regulator high temperature interrupt (hti) acknowledge the interrupt by reading the vo ltage status register - vsr. to issue a new interrupt, the condition has to vanish and occur again. see section 4.5, ?power supply for details on the voltage status register including masking information. 4.7.2.4 low battery interrupt (lbi) acknowledge the interrupt by reading the vo ltage status register - vsr. to issue a new interrupt, the condition has to vanish and occur again. see section 4.5, ?power supply for details on the voltage status register including masking information. 4.7.2.5 tim channel 0 interrupt (ch0) see section 4.19, ?basic time r module - tim (tim16b4c) . 4.7.2.6 tim channel 1 interrupt (ch1) see section 4.19, ?basic time r module - tim (tim16b4c) . 4.7.2.7 tim channel 2 interrupt (ch2) see section 4.19, ?basic time r module - tim (tim16b4c) . 4.7.2.8 tim channel 3 interrupt (ch3) see section 4.19, ?basic time r module - tim (tim16b4c) . 4.7.2.9 tim timer over flow interrupt (tov) see section 4.19, ?basic time r module - tim (tim16b4c) . 4.7.2.10 sci error interrupt (err) see section 4.16, ?serial communication interface (s08sciv4) . 4.7.2.11 sci transmit interrupt (tx) see section 4.16, ?serial communication interface (s08sciv4) . 4.7.2.12 sci receive interrupt (rx) see section 4.16, ?serial communication interface (s08sciv4) . 4.7.2.13 lin driver over-temperature interrupt (linot) acknowledge the interrupt by reading the li n register - linr. to issue a new interr upt, the condition has to vanish and occur again. see section 4.15, ?lin physical layer interface - lin for details on the lin register including masking information. 4.7.2.14 high side over-temperature interrupt (hsot) acknowledge the interrupt by reading the hi gh side status register - hssr. to issue a new interrupt, the condition has to vanis h and occur again. see section 4.12, ?high side drivers - hs for details on the high side status register including masking information.
interrupts mm912_634 advance information, rev. 4.0 freescale semiconductor 68 4.7.2.15 low side over-temperature interrupt (lsot) acknowledge the interrupt by reading the low side status register - lssr. to issue a new interrupt, the condition has to vanish and occur again. see section 4.13, ?low side drivers - lsx for details on the low side status register including masking information. 4.7.2.16 hsup over-temperature interrupt (hot) acknowledge the interrupt by reading the hall supply register - hs r. to issue a new interrupt, the condition has to vanish and occur again. see section 4.11, ?hall sensor supply output - hsup for details on the hall supply register including masking information. 4.7.2.17 high voltage interrupt (hvi) acknowledge the interrupt by reading the vo ltage status register - vsr. to issue a new interrupt, the condition has to vanish and occur again. see section 4.5, ?power supply for details on the voltage status register including masking information. 4.7.2.18 voltage regulator over-voltage interrupt (vrovi) acknowledge the interrupt by reading the vo ltage status register - vsr. to issue a new interrupt, the condition has to vanish and occur again. see section 4.5, ?power supply for details on the voltage status register including masking information.
resets mm912_634 advance information, rev. 4.0 freescale semiconductor 69 4.8 resets to protect the system during critical events, the mm912_634 analog die will drive the reset_a pin low during the presence of the reset condition. in addition, the reset_a pin is monitored for external reset events. to match the mcu, the reset_a pin is based on the vddx voltage level. after an internal reset condition has gone, the reset_a will stay low for an additional time t rst before being released. entering reset mode will cause all mm912_634 analog die re gisters to be initialized to their reset defa ult. the only registers with valid information are t he reset status register (rsr) and the wake-up source register (wus). 4.8.1 reset sources in the mm912_634 six reset sources exist. 4.8.1.1 por - analog die power on reset to indicate the device power supply (vs1) was below vpor or the mm912_634 analog die was powered up, the por condition is set. see section 4.4, ?modes of operation . 4.8.1.2 lvr - low voltage reset - vdd with the vdd voltage regulator output voltage falling below vl vr, the low voltage reset condition becomes present. as the vdd regulator is shutdown once a lvrx condition is detected, the actual cause could be also a low voltage condition at the vddx regulator. see section 4.5, ?power supply . 4.8.1.3 lvrx - low voltage reset - vddx with the vddx voltage regulator output voltage falling below vlvrx, the low voltage reset condition becomes present. see section 4.5, ?power supply . 4.8.1.4 wur - wake-up reset while in sleep mode, any active wake-up event will cause a mm912_634 analog die transition from sleep to reset mode. to determine the wake-up source, refer to section 4.9, ?wake-up / cyclic sense . 4.8.1.5 exr - external reset any low level voltage at the reset_a pin with a duration > trstdf will issue an external reset event. this reset source is also active in stop mode. 4.8.1.6 wdr - watchdog reset any incorrect serving if the mm912_634 analog die watchdog will result in a watchdog reset. please refer to the section 4.10, ?window watchdog for details. 4.8.2 register definition 4.8.2.1 reset status register (rsr) table 92. reset status register (rsr) offset (67) 0x15 access: user read 76543210 r 0 0 wdr exr wur lvrx lvr por w note: 67. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. analog mcu
resets mm912_634 advance information, rev. 4.0 freescale semiconductor 70 reading the reset status register will clear the information in side. writing has no effect. lvr and lvrx are masked when por or wur are set. table 93. rsr - register field descriptions field description 5 - wdr watchdog reset - reset caused by an incorrect serving of the watchdog. 4 - exr external reset - reset caused by the reset_a pin driven low externally for > trstdf. 3 - wur wake-up reset - reset caused by a wake-up from sleep mode. to determine the wake-up source, refer to section 4.9, ?wake-up / cyclic sense . 2 - lvrx low voltage reset vddx - reset caused by a low voltage condition monitored at the vddx output. 1 - lvr low voltage reset vdd - reset caused by a low voltage condition monitored at the vdd output. (68) 0 - por power on reset - supply voltage was below v por . note: 68. as the vdd regulator is shutdown once a lvrx condition is detected, the actual cause could be al so a low voltage condition a t the vddx regulator.
wake-up / cyclic sense mm912_634 advance information, rev. 4.0 freescale semiconductor 71 4.9 wake-up / cyclic sense to wake-up the mm912_634 analog die from stop or sleep mode, several wake-up sources are implemented. as described in section 4.4, ?modes of operation , a wake-up from stop mode will result in an interrupt (d2dint) to the mcu combined with a transition to normal mode. a wake-up from sleep mode will result in a transition to reset mode. in any case, the source of the wake-up can be identified by reading the wake-up source register (wsr). the wake-up source register (wsr) has to be read after a wake-up condition in order to execute a new stop mode command. two base clock cycles (f base ) delay are required between the wsr read and mcr write. in general, there are the follo wing seven main wake-up sources: ? wake-up by a state change of one of the lx inputs ? wake-up by a state change of one of the lx inputs during a cyclic sense ? wake-up due to a forced wake-up ? wake-up by the lin module ? wake-up by d2d interface (stop mode only) ? wake-up due to internal / external reset (stop mode only) ? wake-up due to loss of supply voltage (sleep mode only) figure 19. wake-up sources 4.9.1 wake-up sources 4.9.1.1 lx - wake-up (cyclic sense disabled) any state digital change on a wake-up enabled lx input will issue a wake-up. in order to select and activate a wake-up input (lx), the wake-up control register (wcr) must be configured with appr opriate lxwe inputs enabled or disabled before entering low power mode. the lx - wake-up may be combined with the forced wake-up. note: selecting a lx input for wake-up will disable a selected analog input once entering low power mode. 4.9.1.2 lx - cyclic sense wake-up to reduce external power consumption during low power mode a cyclic wake-up has been implemented. configuring the timing control register (tcr) a specific cycle time can be selected to implement a per iodic switching of the hs1 or hs2 output with th e corresponding detection of an lx state chan ge. any configuration of the hsx in the high side control register (hscr) will be ignored when entering low power mode. the lx - cyclic sens e wake-up may be combined with the forced wake-up. in case both (forced and lx change) events are pr esent at the same time, the forced wake -up will be indicated as wake-up source. note once cyclic sense is configured (cssel!=0), the state change is only recognized from one cyclic sense event to the next. the additional accuracy of the cyclic sense cycle by the wd clock trimming is only active during stop mode. there is no tri mmed clock available during sleep mode. analog mcu lin bus hs1 hs2 l1 l2 l3 l4 l5 v sup lin d2dint d2dclk d2d3 d2d2 d2d1 d2d0 wake up module d2d wake up lin wake up lx ? wake up cyclic sense / forced wake up timer forced wake up cyclic wake up l0
wake-up / cyclic sense mm912_634 advance information, rev. 4.0 freescale semiconductor 72 4.9.1.3 forced wake-up configuring the forced wake-up multiplier (fwm) in the timing control register (t cr) will enable the forced wake-up based on the selected cyclic sense timing (cst). forced wake-up can be combined with all other wake-up sources considering the timing dependencies. 4.9.1.4 lin - wake-up while in low-power mode the mm912_634 analog die monitors t he activity on the lin bus. a dominant pulse longer than t propwl followed by a dominant to recessive transition will cause a lin wake-up. this behavior protects the system from a short-to-ground bus condition. 4.9.1.5 d2d - wake-up (stop mode only) receiving a normal mode request via the d2d interface (mode=0, mode control register (mcr)) will result in a wake-up from stop mode. as this condition is contro lled by the mcu, no wake-up status bit does indicate this wake-up source. 4.9.1.6 wake-up due to internal / external reset (stop mode only) while in stop mode, a reset due to a vdd low voltage condition or an external reset applied on the reset_a pin will result in a wake-up with immediate transition to reset mode. in this case , the lvr or exr bits in the reset status register will indicate the source of the event. 4.9.1.7 wake-up due to loss of supply voltage (sleep mode only) while in sleep mode, a supply voltage vs1 < vpor will result in a transition to power on mode. 4.9.2 register definition 4.9.2.1 wake-up control register (wcr) table 94. wake-up control register (wcr) offset (69) 0x12 access: user read/write 76543210 r cssel l5we l4we l3we l2we l1we l0we w reset00111111 note: 69. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 95. wcr - regist er field descriptions field description 7-6 cssel cyclic sense select - configures the hsx output for the cycl ic sense event. note, with no lx we selected - only the selected hsx output will be switched periodically, no lx state change woul d be detected. for all confi gurations, the forced wake-up can be activated in parallel in section 4.9.2.2, ?timing control register (tcr) 00 - cyclic sense off 01 - cyclic sense with periodic hs1on 10 - cyclic sense with periodic hs2 on 11 - cyclic sense with periodic hs1 and hs2 on. 5 - l5we wake-up input 5 enabled - l5 wake-up select bit. 0 - l5 wake-up disabled 1 - l5 wake-up enabled 4 - l4we wake-up input 4 enabled - l4 wake-up select bit. 0 - l4 wake-up disabled 1 - l4 wake-up enabled
wake-up / cyclic sense mm912_634 advance information, rev. 4.0 freescale semiconductor 73 4.9.2.2 timing control register (tcr) 3 - l3we wake-up input 3 enabled - l3 wake-up select bit. 0 - l3wake-up disabled 1 - l3 wake-up enabled 2- l2we wake-up input 2 enabled - l2 wake-up select bit. 0 - l2 wake-up disabled 1 - l2 wake-up enabled 1 - l1we wake-up input 1 enabled - l1 wake-up select bit. 0 - l1 wake-up disabled 1 - l1 wake-up enabled 0 - l0we wake-up input 0 enabled - l0 wake-up select bit. 0 - l0 wake-up disabled 1 - l0 wake-up enabled table 96. timing control register (tcr) offset (70) 0x13 access: user read/write 76543210 r fwm cst w reset00000000 note: 70. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 95. wcr - regist er field descriptions field description
wake-up / cyclic sense mm912_634 advance information, rev. 4.0 freescale semiconductor 74 4.9.2.3 wake-up source register (wsr) table 97. tcr - regist er field descriptions field description 7-4 fwm forced wake-up multiplicator - configures the multiplicator for the forced wake-up. the selected multiplicator (fwm!=0) will force a wake-up every fwm x cst ms. with this impl ementation, forced and cyclic wake-up can be performed in parallel with the cyclic sense period <= the forced wake-up period. 0000 - forced wake-up = off 0001 - 1x 0010 - 2x 0011 - 4x 0100 - 8x 0101 - 16x 0110 - 32x 0111 - 64x 1000 - 128x 1001 - 256x 1010 - 512x 1011 - 1024x 11xx - not implemented (forced wake multiplicator = 1024x) 3-0 cst cyclic sense timing (71) 0000 - 1.0 ms 0001 - 2.0 ms 0010 - 5.0 ms 0011 - 10 ms 0100 - 20 ms 0101 - 50 ms 0110 - 100 ms 0111 - 200 ms 1000 - 500 ms 1001 - 1000 ms 1010 - 1111 - not implemented (cyclic sense timing = 1000 ms) note: 71. cyclic sense timing wi th accuracy csac and csact. table 98. wake-up source register (wsr) offset (72) 0x14 access: user read 76543210 r fwu linwu l5wu l4wu l3wu l2wu l1wu l0wu w note: 72. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 99. wsr - register field descriptions field description 7 - fwu forced wake-up - wake-up caused by a forced wake-up 6 - linwu lin wake-up - wake-up caused by a lin wake-up 5 - l5wu l5 wake-up - wake-up caused by a state change of the l6 input 4 - l4wu l4 wake-up - wake-up caused by a state change of the l5 input 3 - l3wu l3 wake-up - wake-up caused by a state change of the l4 input
mm912_634 advance information, rev. 4.0 freescale semiconductor 75 reading the wsr will clear the wake-up status bit(s). writing will ha ve no effect. the wake-up source register (wsr) has to be read after a wake-up condition, in or der to execute a new stop mode comma nd. two base clock cycles (fbase) delays are required between the wsr read and the mcr write. 2 - l2wu l2 wake-up - wake-up caused by a state change of the l3 input 1 - l1wu l1 wake-up - wake-up caused by a state change of the l2 input 0 - l0wu l0 wake-up - wake-up caused by a state change of the l1 input table 99. wsr - register field descriptions field description
window watchdog mm912_634 advance information, rev. 4.0 freescale semiconductor 76 4.10 window watchdog the mm912_634 analog die includes a configurable window watchdog, which is active in normal mode. the watchdog module is based on a separate clock source (f base ) operating independent from the mcu based d2dclk clock. the watchdog timeout (t wdto ) can be configured between 10 ms and 1280 ms (typ.) using the watchdog register (wdr). during low power mode, the watchdog feature is not active , a d2d read during stop mode will have the wdoff bit set. to clear the watchdog counter, a alternating write must be perf ormed to the watchdog service register (wdsr). the first write after the reset_a has been released has to be 0xaa. the next one must be 0x55. after the reset_a has been released, there will be a standard (non-windo w) watchdog active with a fixed timeout of tiwdto. the watchdog window open (wdwo) bit is set during that time and the window watchdog can be configured (wdr) without changing the initial timeout, and can be trimmed using the trim value given in the mcu trimming flash section. see section 4.26, ?mm912_634 - analog die trimming . figure 20. mm912_634 analog die watchdog operation to enable the window watchdog, the initial counter reset has to be performed by writing 0xaa to the watchdog service register (wdsr) before tiwdto is reached. if the tiwdto timeout is reache d with no counter reset or a value different from 0xaa was written to the wdsr, a watchdog reset will occur. once entering window watchdog mode, the first half of the time t wdto forbids a counter reset. to reset the watchdog counter, an alternating write of 0x55 and 0xaa must be performed within the second half of the t wdto . a window open (wdwo) flag will indicate the current status of the window. a timeout or wr ong value written to the wdsr will force a watchdog reset. for debug purpose, the watchdog can be completely disabled by applying vtst to the tclk pin while test_a is grounded. the watchdog will be disabled as long as vtst is present. the watchdog is guaranteed functional for vtsten. the wdoff bit will indicate the watchdog being disabled. the wdsr register will reset to default once the watchdog is disabled. once the watchdog is re-enabled, the initial watchdog sequence has to be performed. during low power mode, the watchdog clock is halted and the watc hdog service register (wdsr) is reset to the default state. 4.10.1 register definition 4.10.1.1 watchdog register (wdr) table 100. watchdog register (wdr) offset (73) 0x10 access: user read/write 76543210 r wdoff wdwo 0 00 wdto w reset00000000 note: 73. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. analog mcu window watch dog window closed window watch dog window open standard initial watch dog (no window) t iwdto wd register write = 0x55 initial wd reg. write = 0xaa reset_a release window watch dog window closed window watch dog window open t wdto / 2 t wdto / 2 window wd timing (t wdto ) t wd register write = 0xaa (to be continued)
window watchdog mm912_634 advance information, rev. 4.0 freescale semiconductor 77 4.10.1.2 watchdog service register (wdsr) table 101. wdr - register field descriptions field description 7 - wdoff watchdog off - indicating the watc hdog module is being disabled externally. 6 - wdwo watchdog window open - indicating the watc hdog window is currently open for counter reset. 2-0 wdto[2:0] watchdog timeout configuration - config uring the watchdog timeout duration t wdto . 000 - 10 ms 001 - 20 ms 010 - 40 ms 011 - 80 ms 100 - 160 ms 101 - 320 ms 110 - 640 ms 111 - 1280 ms table 102. watchdog service register (wdsr) offset (74) 0x11 access: user read/write 76543210 r wdsr w reset01010101 note: 74. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 103. wdsr - register field descriptions field description 7-0 wdsr watchdog service register - writing this register with the correct value (0xaa alternating 0x55) while the window is open will reset the watchdog counter. writing the register wh ile the watchdog is disabled will have no effect.
hall sensor supply output - hsup mm912_634 advance information, rev. 4.0 freescale semiconductor 78 4.11 hall sensor s upply output - hsup to supply hall effect sensors or similar external l oads, the hsup output is im plemented. to reduce power dissipation inside the device, the output is implemented as a switchable voltage regulator, internally connected to the vs1 supply input. for protecti on, an over-temperature shutdown and a current limitation is implemented. a write to the hall supply register (hsr), when the over-temperature condition is gone, will re-enable the hall supply output. the hsup output is active only during normal mode. a capacitor chsup is recommended for operation. 4.11.1 register definition 4.11.1.1 hall supply register (hsr) table 104. hall supp ly register (hsr) offset (75) 0x38 access: user read/write 76543210 r hotie hotc 0 0000 hsupon w reset00000000 note: 75. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 105. hsr - register field descriptions field description 7 - hotie hall supply over-temperature interrupt enable 6 - hotc hall supply over-temperature condition present. during the event, the hall supply is shut down. reading the register will clear the hot flag if present. see section 4.7, ?interrupts for details. 0 - hsupon hall supply on: 0 - hall supply regulator disabled 1 - hall supply regulator enabled analog mcu
high side drivers - hs mm912_634 advance information, rev. 4.0 freescale semiconductor 79 4.12 high side drivers - hs these outputs are two high side driver s, intended to drive small resistive l oads or leds incorporating the following features: ? pwm capability via the pwm module ? open load detection ? current limitation ? over-temperature shutdown (with maskable interrupt) ? high voltage shutdown - hvi (software maskable) ? cyclic-sense, see section 4.9, ?wake-up / cyclic sense 4.12.1 open load detection each high side driver signals an open load condition if the current through the high side is below the open load current thresh old. the open load condition is indicated with the bits hs 1ol and hs2ol in the high side status register (hssr). 4.12.2 current limitation each high side driver has an output current limitation. in comb ination with the over-temperature shutdown the high side drivers are protected against over-curr ent and short-circuit failures. that the driver operates in the current lim itation area is indicated with the bits hs 1cl and hs2cl in the high side status regi ster (hssr). 4.12.3 over-temperature protection (hs interrupt) both high side drivers are protected agains t over-temperature. in over-temperature c onditions, both high side drivers are shut down and the event is latched in the interrupt control module. the shutdown is indicate d as hs interrupt in the interrupt sourc e register (isr). a thermal shutdown of the high side drivers is indicated by setting the hsot bit in the high side status register (hssr). a write to the high side control register (hscr), when the ove r-temperature condition is gone, will re- enable the high side drivers. 4.12.4 high voltage shutdown in case of a high voltage condition (hvi), and if the high vo ltage shutdown is enabled (bit hvsde in the high side control regi ster (hscr) is set), both high side drivers are shut down. a write to the high side control register (hscr), when the high voltage condition is gone, will re-enable the high side drivers. 4.12.5 sleep and stop mode the high side drivers can be enabled to operate in sleep and stop mode for cyclic sensing. see section 4.9, ?wake-up / cyclic sense 4.12.6 pwm capability section 4.14, ?pwm control module (pwm8b2c) 4.12.7 register definition 4.12.7.1 high side control register (hscr) table 106. high side control register (hscr) offset (76) 0x28 access: user read/write 76543210 r hsotie hshvsde pwmcs2 pwmcs1 pwmhs2 pwmhs1 hs2 hs1 w reset00000000 note: 76. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. analog mcu
high side drivers - hs mm912_634 advance information, rev. 4.0 freescale semiconductor 80 4.12.7.2 high side status register (hssr) table 107. hscr - regist er field descriptions field description 7 - hsotie high side over-temperature interrupt enable 6 - hshvsde high side high voltage shutdown. once enabled, both high sides will shut down when a high voltage condition - hvc is present. see section 4.5, ?power supply for the voltage status register. 5 - pwmcs2 pwm channel select hs2 0 - pwm channel 0 selected as pwm channel 1 - pwm channel 1 selected as pwm channel 4 - pwmcs1 pwm channel select hs1 0 - pwm channel 0 selected as pwm channel 1 - pwm channel 1 selected as pwm channel 3 - pwmhs2 pwm enable for hs2 0 - pwm disabled on hs2 1 - pwm enabled on hs2 (channel as selected with pwmcs2) 2 - pwmhs1 pwm enable for hs1 0 - pwm disabled on hs1 1 - pwm enabled on hs1 (channel as selected with pwmcs1) 1 - hs2 hs2 control 0 - hs2 disabled 1 - hs2 enabled 0 - hs1 hs2 control 0 - hs1 disabled 1 - hs1 enabled table 108. high side status register (hssr) offset (77) 0x29 access: user read 76543210 r hsotc 0 0 0 hs2cl hs1cl hs2ol hs1ol w reset00000000 note: 77. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 109. hssr - register field descriptions field description 7 - hsotc high side over-temperature condition present. both drivers ar e turned off. reading the register will clear the hsot interrupt flag if present. see section 4.7, ?interrupts for details. 3 - hs2cl high side 2 current limitation 2 - hs1cl high side 1 current limitation 1 - hs2ol high side 2 open load 1 - hs1ol high side 1open load
low side drivers - lsx mm912_634 advance information, rev. 4.0 freescale semiconductor 81 4.13 low side drivers - lsx 4.13.1 introduction / features these outputs are two low side drivers intended to dr ive relays (inductive loads) incorporating the following features: ? pwm capability ? open load detection ? current limitation ? over-temperature shutdown (with maskable interrupt) ? active clamp ? independent vreg - high voltage shutdown 4.13.1.1 block diagram the following figure shows the basi c structure of the ls drivers. figure 21. low side drivers - block diagram 4.13.1.2 modes of operation the low side module is active only in normal mode; the low side drivers are disabled in sleep and stop mode. 4.13.2 external signal description this section lists and describes the signals that do connect off-chip. table 110 shows all the pins and their functions that are controlled by the low side module. table 110. pin functions and priorities pin name pin function & priority i/o description pin function after reset ls1 high voltage output o low side power output driver, active clamping ls1 ls2 o ls2 analog mcu analog lsx low side - driver (active clamp) open load detection current limitation overtemperture shutdown (maskable interrupt) vreg high voltage shutdown (maskable interrupt) pgnd active clamp interrupt control module lsotie ls - control lsx lsxol lsxcl mode[1:0] high temperature irq on/off status v dd pwmlsx lsotc pwmcsx pwm0 pwm1 vrovc vrovie vreg high voltage irq vreg high voltage lscen[3:0] vdd digital sleep2p5 digital 4 b i t 4bit vreg hv shutdown latch control 1bit located in vcr located in vsr
low side drivers - lsx mm912_634 advance information, rev. 4.0 freescale semiconductor 82 4.13.3 memory map and registers 4.13.3.1 module memory map table 111 shows the register map of the low side driver module. all register addresses given are referenced to the d2d interface offset. 4.13.3.2 register descriptions 4.13.3.2.1 low side co ntrol register (lscr) table 111. low side mo dule - memory map register name bit 7 6 5 4 3 2 1 bit 0 0x30 lscr r lsotie 0 pwmcs2 pwmcs1 pwmls2 pwmls1 ls2 ls1 w 0x31 lssr r lsotc 0 0 0 ls2cl ls1cl ls2ol ls1ol w 0x32 lscen r0000 lscen w table 112. low side control register (lscr) offset (78) 0x30 access: user read/write 76543210 r lsotie 0 pwmcs2 pwmcs1 pwmls2 pwmls1 ls2 ls1 w reset00000000 note: 78. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 113. lscr - register field descriptions field description 7 - lsotie low side over-temperature interrupt enable 5 - pwmcs2 pwm channel select ls2 0 - pwm channel 0 selected as pwm channel 1 - pwm channel 1 selected as pwm channel 4 - pwmcs1 pwm channel select ls1 0 - pwm channel 0 selected as pwm channel 1 - pwm channel 1 selected as pwm channel 3 - pwmls2 pwm enable for ls2 0 - pwm disabled on ls2 1 - pwm enabled on ls2 (channel as selected with pwmcs2) 2 - pwmls1 pwm enable for ls1 0 - pwm disabled on ls1 1 - pwm enabled on ls1 (channel as selected with pwmcs1) 1 - ls2 ls2 enable; lsen has to be written once to control the ls2 driver 0 - ls1 ls1 enable; lsen has to be written once to control the ls1 driver
low side drivers - lsx mm912_634 advance information, rev. 4.0 freescale semiconductor 83 4.13.3.2.2 low side status register (lssr) 4.13.3.2.3 low side control enable register (lscen) 4.13.4 functional description the low side switches are controlled by the bits ls1:2 in the low side control register (lscr). in order to control the low sides, the lscen register has to be corre ctly written once after reset or vrov. to protect the device against over-voltage when an inductive load (relay) is turned off an active clamp circuit is implemented. 4.13.4.1 voltage regulator over-voltage protection to protect the application for an unintentional activation of th e drivers in case of a voltage regulator over-voltage failure, the low side drivers will automatically shut down in case of an over-voltage on one of the two regulators. the shutdown is fully handled in the analog section of the driver . this will secure the feature in case the digital logic is da maged due to the over-voltage condition. table 114. low side status register (lssr) offset (79) 0x31 access: user read 76543210 r lsotc 0 0 0 ls2cl ls1cl ls2ol ls1ol w reset00000000 note: 79. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 115. lssr - register field descriptions field description 7 - lsotc low side over-temperature condition present. both drivers are turned off. reading the register will clear the lsot interrupt flag if present. see section 4.7, ?interrupts for details. 3 - ls2cl low side 2 current limitation 2 - ls1cl low side 1 current limitation 1 - ls2ol low side 2 open load 0 - ls1ol low side 1open load table 116. low side enable register (lsen) offset (80) 0x32 access: user read/write 76543210 r 0 000 lscen w reset00000000 note: 80. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 117. lsen - register field descriptions field description 3-0 lscen low side control enable - to allow the ls control via lsx, t he correct value has to be written into the lscen register. 0x5 - low side control enabled all other values - low side control disabled
low side drivers - lsx mm912_634 advance information, rev. 4.0 freescale semiconductor 84 once an over-voltage condition on one of the voltage regulators occurs, the lsx control bits in the low side control register (lscr) will be reset to 0. the voltage regulator over-voltage co ndition bit (vrovc) in the voltage status register (vsr) will stay set as long as the condition is present. if the voltage r egulator over-voltage interrupt was enabled (vrovie=1), the vrov- interrupt will be issued. reading the voltage regulator over-volt age condition bit (vrovc) in the voltage status register (vsr) will clear the interrupt. to issue another vrov - interrupt, the condition has to vanish and be present again. to re-enable the low side drivers after a voltage regulator over-v oltage condition occurred, first the lscen register has to be written with ?0x05? - this information is processed through the main digital blocks, and would secure a minimum functionality before enabling the ls drivers again. in a se cond step, the lsx control bits in the lo w side control register (lscr) must be enabled again after the over-voltage condition has vanished (vrovc=0). note the over-voltage threshold has to be trim med at system power up. please refer to section 4.26.1.2.3, ?trimming register 2 (ctr2) for details. the default trim is worst case and may have disabled the ls function already. an initial ls enable would be needed. 4.13.4.2 open load detection each low side driver signals an open load condition if the curr ent through the low side is below the open load current threshol d. the open load condition is indicated with the bit ls1o p and ls2op in the low side status register (lssr). 4.13.4.3 current limitation each low side driver has a current limitat ion. in combination with the over-tempera ture shutdown, the low side drivers are protected against over-current and short-circuit failures. the driver operates in current limitation, and is indicated with the bits ls1cl and ls2cl in the low side status register (lssr ). note: if the drivers is operating in current limitation mode excessive power might be dissipated. 4.13.4.4 over-temperature protection (ls interrupt) both low side drivers are protected against over-temperature. in case of an over-temperature condition, both low side drivers are shut down and the event is latched in t he interrupt control module. the shutdown is indicated as ls interrupt in the interr upt source register (isr). if the bit lsm is set in the in terrupt mask register (imr) than an interrupt (irq) is generated. a write to the low side control register (l scr) will re-enable the low side drivers wh en the over-temperature condition is gone . 4.13.5 pwm capability see section 4.14, ?pwm control module (pwm8b2c) .
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 85 4.14 pwm control module (pwm8b2c) 4.14.1 introduction to control the high side (hs1, hs2) and the low side (ls1 , ls2) duty cycle as well as the ptb2 output, the pwm module is implemented. refer to the individual driver se ction for details on the use of the internal pwm1 and pwm0 signal ( section 4.12, ?high side drivers - hs , section 4.13, ?low side drivers - lsx and section 4.18, ?general purpose i/o - ptb[0?2] ) the pwm definition is based on the hc12 pwm definitions with some of the simplifications in corporated. the pwm module has two channels with independent cont rols of left and center aligned outputs on each channel. each of the two channels has a programmable period and duty c ycle as well as a dedicated counter. a flexible clock select scheme allows a total of four different clock sources to be used with the counters. ea ch of the modulators can create independe nt continuous waveforms with software-selectable duty rates from 0% to 100%. 4.14.1.1 features the pwm block includes th ese distinctive features: ? two independent pwm channels with programmable periods and duty cycles ? dedicated counter for each pwm channel ? programmable pwm enable/disable for each channel ? software selection of pwm duty pulse polarity for each channel ? period and duty cycle are double buffer ed. change takes effect when the end of the effective peri od is reached (pwm counter reaches zero), or when the channel is disabled ? programmable center or left ali gned outputs on individual channels ? four clock sources (a, b, sa, and sb) provide for a wide range of frequencies ? programmable clock select logic 4.14.1.2 modes of operation the pwm8b2c module does operate in normal mode only. 4.14.1.3 block diagram figure 22 shows the block diagram for the 8-bit 2-channel pwm block. figure 22. pwm block diagram analog mcu clock select pwm clock period and duty counter channel 1 alignment polarity control pwm8b2c pwm1 enable pwm channels period and duty counter channel 0 pwm0 d2d clock
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 86 4.14.2 signal description the pwm module has a total of two internal outputs to control the low side outputs, the high side outputs and / or the ptb2 output with pulse width modulation. see section 4.12, ?high side drivers - hs , section 4.13, ?low side drivers - lsx and section 4.18, ?general purpose i/o - ptb[0?2] for configuration details. note based on the d2d clock speed, the pwm8b2c module is capable of generating pwm signal frequencies higher than the maximum output frequency of the connected driver (hs, ls). please refer to section 3.6, ?dynamic electrical characteristics for details. do not exceed the driver maximum output frequency! 4.14.2.1 d2dclk die 2 die interface clock. 4.14.2.2 pwm1 ? pulse wi dth modulator channel 1 this signal serves as waveform output of pwm channel 1. 4.14.2.3 pwm0 ? pulse wi dth modulator channel 0 this signal serves as waveform output of pwm channel 0. 4.14.3 register descriptions this section describes in detail all the r egisters and register bits in the pwm modul e. reserved bits within a register will al ways read as 0 and the write will be unimplemented. unimpl emented functions are indi cated by shading the bit. table 118. pwm register summary name / offset (81) 7 6 5 4 3 2 1 0 0x60 pwmctl r cae1 cae0 pclk1 pclk0 ppol1 ppol0 pwme1 pwme0 w 0x61 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x62 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x63 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w 0x64 pwmcnt0 rbit 7 6 5 4 3 2 1 bit 0 w00000000 0x65 pwmcnt1 rbit 7 6 5 4 3 2 1 bit 0 w00000000 0x66 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x67 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x68 pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x69 pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w note: 81. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 87 4.14.3.1 pwm control register (pwmctl) 4.14.3.1.1 pwm enable (pwmex) each pwm channel has an enable bit (pwmex) to start its wave form output. when any of the pw mex bits are set (pwmex = 1), the associated pwm output is enabled immediately. however, th e actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle, du e to the synchronization of pwmex and the clock source. note the first pwm cycle after enabling the channel can be irregular. if both pwm channels are disabled (pwme1?0 = 0), the prescaler counter shuts off for power savings. 4.14.3.1.2 pwm po larity (ppolx) the starting polarity of each pwm channel waveform is determined by the associated ppolx bit. if the polarity bit is one, the pwm channel output is high at the beginning of the cycle and then goes low when the dut y count is reached. conversely, if the polarity bit is zero, the output starts low a nd then goes high when t he duty count is reached. note ppolx register bits can be written anytime. if the polarity changes while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition 4.14.3.1.3 pwm clock select (pclkx) each pwm channel has a choice of two clocks to use as the clock source for that channel as described by the following. table 119. pwm contro l register (pwmctl) offset (82) 0x60 access: user read/write 76543210 r cae1 cae0 pclk1 pclk0 ppol1 ppol0 pwme1 pwme0 w reset00000000 note: 82. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 120. pwmctl - register field descriptions field description 7?6 cae[1:0] center aligned output modes on channels 1?0 0 channels 1?0 operate in left aligned output mode. 1 channels 1?0 operate in center aligned output mode. 5 pclk1 pulse width channel 1 clock select 0 clock b is the clock source for pwm channel 1. 1 clock sb is the clock source for pwm channel 1. 4 pclk0 pulse width channel 0 clock select 0 clock a is the clock source for pwm channel 0. 1 clock sa is the clock source for pwm channel 0. 3?2 ppol[1:0] pulse width channel 1?0 polarity bits 0 pwm channel 1?0 outputs are low at the beginning of the period, then go high when the duty count is reached. 1 pwm channel 1?0 outputs are high at the beginning of the period, then go low when the duty count is reached. 1-0 pwme[1:0] pulse width channel 1?0 enable 0 pulse width channel 1?0 is disabled. 1 pulse width channel 1?0 is enabled. the pulse modulated si gnal becomes available at pw m, output bit 1 when its clock source begins its next cycle.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 88 note register bits pclk0 and pclk1 can be written anytime. if a clock se lect changes while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 4.14.3.1.4 pwm center align enable (caex) the caex bits select either center aligned outputs or left ali gned output for both pwm channels. if the caex bit is set to a on e, the corresponding pwm output will be center aligned. if the caex bit is cleared, the corresponding pwm output will be left aligned. see section 4.14.4.2.5, ?left aligned outputs? and section 4.14.4.2.6, ?center aligned outputs? for a more detailed description of the pwm output modes. note write these bits only when the corresponding channel is disabled. 4.14.3.2 pwm prescale clock select register (pwmprclk) this register selects the prescale clock source for clocks a and b independently. table 121. pwm prescale clock select register (pwmprclk) offset (83) 0x61 access: user read/write 76543210 r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w reset00000000 note: 83. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 122. pwmprclk - register field descriptions field description 6?4 pckb[2:0] prescaler select for clock b ? clock b is one of two clock sources which can be used for channel 1. these three bits determine the rate of clock b, as shown in table 123 . 2?0 pcka[2:0] prescaler select for clock a ? clock a is one of two clock sources which can be used for channel 0. these three bits determine the rate of clock a, as shown in table 124 . table 123. clock b prescaler selects pckb2 pckb1 pckb0 value of clock b 0 0 0 d2d clock 0 0 1 d2d clock / 2 0 1 0 d2d clock / 4 0 1 1 d2d clock / 8 1 0 0 d2d clock / 16 1 0 1 d2d clock / 32 1 1 0 d2d clock / 64 1 1 1 d2d clock / 128
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 89 note pckb2?0 and pcka2?0 register bits can be wr itten anytime. if the clock pre-scale is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 4.14.3.3 pwm scale a register (pwmscla) pwmscla is the programmable scale value used in scaling clock a to generate clock sa. clock sa is generated by taking clock a, dividing it by the value in the pwmscla register and dividing that by two. clock sa = clock a / (2 * pwmscla) note when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmscla) . 4.14.3.4 pwm scale b register (pwmsclb) pwmsclb is the programmable scale value used in scaling clock b to generate clock sb. clock sb is generated by taking clock b, dividing it by the value in the pwmsclb register and dividing that by two. clock sb = clock b / (2 * pwmsclb) note when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmsclb). table 124. clock a prescaler selects pcka2 pcka1 pcka0 value of clock a 00 0 d2d clock 0 0 1 d2d clock / 2 0 1 0 d2d clock / 4 0 1 1 d2d clock / 8 1 0 0 d2d clock / 16 1 0 1 d2d clock / 32 1 1 0 d2d clock / 64 1 1 1 d2d clock / 128 table 125. pwm scale a register (pwmscla) offset (84) 0x62 access: user read/write 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset00000000 note: 84. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 90 4.14.3.5 pwm channel counter registers (pwmcntx) each channel has a dedicated 8-bit up/down counter, which runs at the rate of the selected clock source. the counter can be read at any time without affecting the count or the operation of the pwm channel. in left ali gned output mode, the counter coun ts from 0 to the value in the period register - 1. in center aligned output mode, the co unter counts from 0 up to the value in the period register and then back down to 0. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. the counte r is also cleared at the end of the effective period (see section 4.14.4.2.5, ?left aligned outputs? and section 4.14.4.2.6, ?center aligned outputs? for more details). when the channel is disabled (pwm ex = 0), the pwmcntx regist er does not count. when a channel becomes enabled (pwmex = 1), the associated pwm counte r starts at the count in the pwmcntx register. for more detailed information on the operation of the counters, see section 4.14.4.2.4, ?pwm timer counters? . note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. 4.14.3.6 pwm channel period registers (pwmperx) there is a dedicated period register for ea ch channel. the value in this register determines the period of the associated pwm channel. the period registers for each channel are double buffered, so if they change while the channel is enabled, the change will not take effect until one of the following occurs: ? the effective period ends ? the counter is written (counter resets to $00) ? the channel is disabled in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writ es to the period register will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active period due to the double buffering scheme. see section 4.14.4.2.3, ?pwm period and duty? for more information. to calculate the output period, take the se lected clock source period for the channel of interest (a, b, sa, or sb) and multipl y it by the value in the period register for that channel: table 126. pwm scale b register (pwmsclb) offset (85) 0x63 access: user read/write 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset00000000 note: 85. offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 127. pwm channel counter registers (pwmcntx) offset (86) 0x64/0x65 access: user read/write 76543210 rbit 7 6 5 4 3 2 1 bit 0 w00000000 reset00000000 note: 86. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 91 ? left aligned output (caex = 0) ? pwmx period = channel clock period * pwmperx center aligned output (caex = 1) ? pwmx period = channel clock period * (2 * pwmperx) for boundary case programming values, please refer to section 4.14.4.2.7, ?pwm boundary cases? . 4.14.3.7 pwm channel duty registers (pwmdtyx) there is a dedicated duty register for eac h channel. the value in this register determines the duty of the associated pwm channel. the duty value is compared to the counter and if it is equal to the counter value a match occurs and the output change s state. the duty registers for each channel are double buffered, so if they change while the channel is enabled, the change will not take effect until one of the following occurs: ? the effective period ends ? the counter is written (counter resets to $00) ? the channel is disabled in this way, the output of the pwm will always be either the old duty waveform or the new duty wa veform, not some variation in between. if the channel is not enabled, then writes to the duty regi ster will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active duty due to the double buffering scheme. see section 4.14.4.2.3, ?pwm period and duty? for more information. note depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. if the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers cont ain a count of the high time. if the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. to calculate the output duty cycle (high time as a% of period) for a particular channel: ? polarity = 0 (ppol x =0) ? duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% ? polarity = 1 (ppolx = 1) ? duty cycle = [pwmdtyx / pwmperx] * 100% for boundary case programming values, please refer to section 4.14.4.2.7, ?pwm boundary cases? . table 128. pwm channel period registers (pwmperx) offset (87) 0x66/0x67 access: user read/write 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset00000000 note: 87. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 129. pwm channel duty registers (pwmdtyx) offset (88) 0x68/0x69 access: user read/write 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset00000000 note: 88. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 92 4.14.4 functional description 4.14.4.1 pwm clock select there are four available clocks: clock a, clock b, clock sa (scaled a), and clock sb ( scaled b). these four clocks are based on the d2d clock. clock a and b can be software selected to be 1, 1/2, 1/4, 1/8,. .., 1/64, 1/128 times the d2d clock. clock sa uses clock a as an input and divides it further with a reloadable counter. similarly, clock sb uses clock b as an input and divides it further wit h a reloadable counter. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for cl ock sb. each pwm channel has the capability of selecting one of tw o clocks, either the pre-scaled clock (clock a or b) or the scaled clock (clock sa or sb). the block diagram in figure 23 shows the four different clocks and how the scaled clocks are created. 4.14.4.1.1 prescale the input clock to the pwm prescaler is the d2d clock. the input clock can also be disabled when both pwm channels are disabled (pwme1-0 = 0). this is useful for reducing power by disabling the prescale counter. clock a and clock b are scaled values of the input clock. the value is software selectable for both clock a and clock b and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/12 8 times the d2d clock. the value sele cted for clock a is determined by th e pcka2, pcka1, pcka0 bits in the pwmprclk register. the value selected for clock b is determined by the pckb2, pckb1, pckb0 bits also in the pwmprclk register. 4.14.4.1.2 clock scale the scaled a clock uses clock a as an input and divides it furt her with a user programmable valu e and then divides this by 2. the scaled b clock uses clock b as an input and divides it furt her with a user programmable valu e and then divides this by 2. the rates available for clock sa are software selectable to be cloc k a divided by 2, 4, 6, 8,..., or 512 in increments of divid e by 2. similar rates are available for clock sb.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 93 figure 23. pwm clock select block diagram clock a is used as an input to an 8-bit down counter. this down counter loads a user programmable scale value from the scale register (pwmscla). when the down counter reaches one, a pulse is outp ut and the 8-bit counter is re-loaded. the output signal from this circuit is further divided by two. this gives a grea ter range with only a slight reduction in granularity. clock sa e quals clock a divided by two times the value in the pwmscla register. 128 248163264 pckb2 pckb1 pckb0 m u x clock a clock b clock sa clock a/2, a/4, a/6,....a/512 prescale scale divide by d2d clock clock select m u x pclk0 clock to pwm ch 0 m u x pclk1 clock to pwm ch 1 load div 2 pwmsclb clock sb clock b/2, b/4, b/6,....b/512 m u x pcka2 pcka1 pcka0 pwme1-0 count = 1 load div 2 pwmscla count = 1 8-bit down counter 8-bit down counter prescaler taps:
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 94 note clock sa = clock a / (2 * pwmscla) when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. similarly, clock b is used as an input to an 8-bit down counter followed by a divide by two producing clock sb. thus, clock sb equals clock b divided by two times the value in the pwmsclb register. note clock sb = clock b / (2 * pwmsclb) when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. as an example, consider the case in whic h the user writes $ff into the pwmscla register. clock a for this case will be e divide d by 4. a pulse will occur at a rate of onc e every 255x4 e cycles. passing this through the divide by two circuit produces a cloc k signal at an e divided by 2040 rate. similarly, a value of $01 in the pwmscla register when clock a is e divided by 4 will prod uce a clock at an e divided by 8 rate. writing to pwmscla or pwmsclb causes the associated 8-bit down counter to be re-loaded. otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. forcin g the associated counter to re-load the scale register value every time pwmscla or pwmsclb is written prevents this. note writing to the scale registers while channels are operating can cause irregularities in the pwm outputs. 4.14.4.1.3 clock select each pwm channel has the capability of selecting one of two cloc ks. for channels 0 the clock choice is clock a or clock sa. for channels 1 the choice is clock b or clock sb. the clock selection is done with the pc lkx control bits in the pwmctl register. note changing clock control bits while channels are operating can cause irregularities in the pwm outputs. 4.14.4.2 pwm channel timers the main part of the pwm module are the actual timers. each of the timer channels has a counter, a period register, and a duty register (each are 8-bit). the waveform output period is controll ed by a match between the period register and the value in the counter. the duty is controlled by a match between the duty register a nd the counter value, and caus es the state of the output to change during the period. the starting polar ity of the output is also selectable on a per channel basis. shown in figure 24 is the block diagram for the pwm timer.
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 95 figure 24. pwm timer channel block diagram 4.14.4.2.1 pwm enable each pwm channel has an enable bit (pwmex) to start its wave form output. when any of the pw mex bits are set (pwmex = 1), the associated pwm output signal is enabled immediately. howe ver, the actual pwm waveform is not available on the associated pwm output until its clock sour ce begins its next cycle due to the synchro nization of pwmex and the clock source. note the first pwm cycle after enablin g the channel can be irregular. on the front end of the pwm timer, the clock is enabled to the pwm circuit by the pwmex bit being high. there is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. when the channel is disable d (pwmex = 0), the counter for the channel does not count. 4.14.4.2.2 pwm polarity each channel has a polarity bit to allow st arting a waveform cycle with a high or low signal. this is shown on the block diagra m as a mux select of either the q output or the q output of the pwm output flip flop. when one of the bits in the pwmpol register is set, the associated pwm channel outp ut is high at the beginning of the wave form, then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then g oes high when the duty count is reached. 4.14.4.2.3 pwm pe riod and duty dedicated period and duty registers exist for each channel and are double buffered, so if they change while the channel is enabled, the change will not take effect until one of the following occurs: ? the effective period ends ? the counter is written (counter resets to $00) ? the channel is disabled d2d clock t r q q ppolx pwmex pwm gate 8-bit compare = pwmdtyx 8-bit compare = pwmperx caex t r q q 8-bit counter pwmcntx (clock edge sync) up /down reset m u x
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 96 in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period and dut y registers will go directly to the latches as well as the buff er. a change in duty or period can be forced into effect ?immediate ly? by writing the new value to the duty and/or period registers , and then writing to the counter. this forces the counter to rese t and the new duty and/or period values to be latched. in addit ion, since the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be us ed to make adjustments note when forcing a new period or duty into effect immediately, an irregular pwm cycle can occur. depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. 4.14.4.2.4 pwm timer counters each channel has a dedicated 8-bit up/down counter whic h runs at the rate of the selected clock source (see section 4.14.4.1, ?pwm clock select? for the available clock sources and rates). the counte r compares to two registers, a duty register and a period register as shown in figure 24 . when the pwm counter matches the duty regi ster, the output flip-f lop changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register behaves differently depending on what output mode is selected as shown in figure 24 and described in section 4.14.4.2.5, ?l eft aligned outputs? and section 4.14.4.2.6, ?center aligned outputs? . each channel counter can be read at anytime without af fecting the count or the oper ation of the pwm channel. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values fr om the buffers, and the output to change according to the polarity bit. when the channel is disabled (pwmex = 0), the counter stops. when a channel becomes enabled (pwmex = 1), the associated pwm counter continues from the count in the pw mcntx register. this allows the waveform to continue where it left off when the channel is re-enabled. when the channel is disabled, writing ?0? to the period register will caus e the counter to reset on the next selected clock. note to start a new ?clean? pwm waveform without any ?history? from the old waveform, writing the channel counter (pwmcntx) must happen prior to enabling the pwm channel (pwmex = 1). generally, writes to the counter are done prior to enabling a chan nel in order to start from a known state. however, writing a counter can also be done while the pwm channel is enabled (co unting). the effect is similar to writing the counter when the channel is disabled, except that the new period is started i mmediately with the output set according to the polarity bit. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. the counter is cleared at the end of the effective period (see section 4.14.4.2.5, ?l eft aligned outputs? and section 4.14.4.2.6, ?center aligned outputs? for more details). 4.14.4.2.5 left al igned outputs the pwm timer provides the choice of two types of outputs, left aligned or center aligned. they are selected with the caex bits in the pwmctl register. if the caex bit is cleared (caex = 0), the corresponding pwm output will be left aligned. in left aligned output mode, the 8-bit c ounter is configured as an up counter only. it compares to two registers, a duty regist er and a period register as shown in the block diagram in figure 24 . when the pwm counter matches the duty register the output flip-flop changes state causing the pwm waveform to also change stat e. a match between the pwm counter and the period register resets the counter and the output flip-flop, as shown in figure 24 , as well as performing a load from the double buffer period and duty register to the associat ed registers, as described in section 4.14.4.2.3, ?pwm period and duty? . the counter counts from 0 to the value in the period register ? 1. table 130. pwm timer counter conditions counter clears ($00) counter counts counter stops when pwmcntx register written to any value when pwm channel is enabled (pwmex = 1). counts from last value in pwmcntx. when pwm channel is disabled (pwmex = 0) effective period ends
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 97 note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregul arities in the pwm output. it is recommended to program the output mode befo re enabling the pwm channel. figure 25. pwm left aligned output waveform to calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequenc y for the channel (a, b, sa, or sb), and divide it by the value in the period register for that channel. ? pwmx frequency = clock (a, b, sa, or sb) / pwmperx ? pwmx duty cycle (high time as a % of period): ? polarity = 0 (ppolx = 0) ? duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% ? polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a left aligned output, consider the following case: clock source = e, where e = 10 khz (100 s period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 khz/4 = 2.5 khz pwmx period = 400 s pwmx duty cycle = 3/4 *100% = 75% the output waveform generated is shown in figure 26 . figure 26. pwm left aligned output example waveform 4.14.4.2.6 center aligned outputs for a center aligned output mode selection, set the caex bi t (caex = 1) in the pwmctl register, and the corresponding pwm output will be center aligned. the 8-bit counter operates as an up/down count er in this mode, and is set to up whenev er the counter is equal to $00. the count er compares to two registers, a duty register and a pe riod register, as shown in the block diagram in figure 24 . when the pwm counter matches the duty register, the outpu t flip-flop changes state, causing the pw m waveform to also change state. a match between the pwm counter and the period regi ster changes the counter di rection from an up-count to a down-count. when the pwm counter decrements and matches the duty register again, the output flip-flop chan ges state, causing the pwm output to also change state. when the pwm counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count, and a load from the double buffer period and duty registers to the associated regi sters is performed, as descri bed pwmdtyx period = pwmperx ppolx = 0 ppolx = 1 period = 400 s e=100s duty cycle = 75%
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 98 in section 4.14.4.2.3, ?pwm period and duty? . the counter counts from 0 up to the val ue in the period register and then back down to 0. thus the effective period is pwmperx*2. note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregul arities in the pwm output. it is recommended to program the output mode befo re enabling the pwm channel. figure 27. pwm center aligned output waveform to calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source freque ncy for the channel (a, b, sa, or sb) and divide it by twice the value in the period register for that channel. ? pwmx frequency = clock (a, b, sa, or sb) / (2*pwmperx) ? pwmx duty cycle (high time as a% of period): ? polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% ? polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a center aligned output, consider the following case: clock source = e, where e = 10 khz (100 s period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 khz/8 = 1.25 khz pwmx period = 800 s pwmx duty cycle = 3/4 *100% = 75% figure 28 shows the output waveform generated. figure 28. pwm center aligned output example waveform 4.14.4.2.7 pwm boundary cases table 131 summarizes the boundary conditions for the pwm, regardle ss of the output mode (left aligned or center aligned). ppolx = 0 ppolx = 1 pwmdtyx pwmdtyx period = pwmperx*2 pwmperx pwmperx e=100s duty cycle = 75% e=100s period = 800 s
pwm control module (pwm8b2c) mm912_634 advance information, rev. 4.0 freescale semiconductor 99 4.14.5 resets the reset state of each individual bit is listed within the section 4.14.3, ?register descriptions? , which details the registers and their bit-fields. all special functions or modes which are init ialized during or just following reset are described within this section. ? the 8-bit up/down counter is configur ed as an up counter out of reset. ? all the channels are disabled and all the counters do not count. 4.14.6 interrupts the pwm module has no interrupts. table 131. pwm boundary cases pwmdtyx pwmperx ppolx pwmx output $00 (indicates no duty) >$00 1 always low $00 (indicates no duty) >$00 0 always high xx $00 (89) (indicates no period) 1 always high xx $00 (89) (indicates no period) 0 always low >= pwmperx xx 1 always high note: 89. counter = $00 and does not count.
lin physical layer interface - lin mm912_634 advance information, rev. 4.0 freescale semiconductor 100 4.15 lin physical la yer interface - lin the lin bus pin provides a physical layer for single-wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer version 2.1 specific ation, and has the following features: ? lin physical la yer 2.1 compliant ? slew rate selection 20 kbit, 10 kbit, and fast mode (100 kbit) ? over-temperature shutdown - hti ? permanent pull-up in normal mode 30 k ? , 1.0 m ? in low power ? current limitation ? external rx / tx access. see section 4.18, ?general purpose i/o - ptb[0?2] ? slew rate trim bit. see section 4.26, ?mm912_634 - analog die trimming the lin driver is a low side mosfet with current limitation and t hermal shutdown. an internal pull-up resistor with a serial di ode structure is integrated, so no external pull-up components are required for the applicat ion in a slave node. the fall time from dominant to recessive and the rise time from recessive to dominant is controll ed. the symmetry between both slopes is guaranteed. 4.15.1 lin pin the lin pin offers high susceptibility immunity level from exte rnal disturbance, guaranteeing communication during external disturbance. see section 3.8, ?esd protection and latch-up immunity . 4.15.2 slew ra te selection the slew rate can be selected for optimized op eration at 10 kbit/s and 20 kbit /s as well as a fast baud rate (100 kbit) for test a nd programming. the slew rate can be adapted wi th the bits linsr[1:0] in t he lin register (linr). the initial slew rate is 20 kbit/ s. 4.15.3 over-temperature shutdown (lin interrupt) the output low side fet (transmitter) is protected against over-temperature cond itions. in case of an over-temperature condition, the transmitter will be shut down and the bit linotc in the li n register (linr) is set as long as the condition is present. if the linotie bit is set in the lin regi ster (linr), an interrupt irq will be generat ed. acknowledge the interrupt by reading the lin register (linr). to issue a new interrup t, the condition has to vanish and occur again. the transmitter is automatically re-enabled once the ov er-temperature condition is gone and txd is high. 4.15.4 low power mode and wake-up feature during low power mode operation the transmitter of the physical layer is disabled. the receiver is still active and able to det ect wake-up events on the lin bus line. a dominant level longer than t propwl followed by a rising edge, will generate a wa ke-up event and be reported in the wake-up source register (wsr). 4.15.5 j2602 compliance a low voltage shutdown feature was implemented to allow cont rolled j2602 compliant lin driver behavior under low voltage conditions (lvsd=0). when an under-voltage occurs on vs1 (lvi), the lin stays in recessive mode if it was in recessive state. if it was in a dominan t state, it waits until the next dominant to recessive transition, then it sta ys in the recessive state. when the under-voltage condition (lvi) is gone, the lin will start operating when tx is in a recessive state or on the next dom inant to recessive transition. analog mcu
mm912_634 advance information, rev. 4.0 freescale semiconductor 101 4.15.6 register definition 4.15.6.1 lin register (linr) table 132. lin register (linr) offset (90) 0x18 access: user read 76543210 r linotie linotc rx tx lvsd linen linsr w reset00000000 note: 90. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 133. linr - register field descriptions field description 7 - linotie lin - over-temperature interrupt enable 6 - linotc lin - over-temperature condition pr esent. lin driver is shut down. reading th is bit will clear the linot interrupt fl ag. 5 - rx lin - receiver (rx) status. 0 - lin bus dominant 1 - lin bus recessive 4 - tx lin - direct transmitter control. the inverted signal is or 0 - transmitter not controlled 1 - transmitter dominant 3 - lvsd lin - low voltage shutdown disable (j2602 compliance control) 0 - lin will be set to recessive state in case of vs1 under-voltage condition 1 - lin will stay functional ev en with a vs1 under-voltage condition 2 - linen lin module enable 0 - lin module disabled 1 - lin module enabled 1-0 - linsr lin - slew rate select 00 - normal slew rate (20 kbit) 01 - slow slew rate (10.4 kbit) 10 - fast slew rate (100 kbit) 11 - normal slew rate (20 kbit)
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 102 4.16 serial communicati on interface (s08sciv4) 4.16.1 introduction 4.16.1.1 features features of the sci module include: ? full-duplex, standard non-return-to-zero (nrz) format ? double-buffered transmitter and receiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing error, and noise error ? idle receiver detect ? active edge on receive pin ? break detect supporting lin ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver wake-up by idle-line or address-mark ? optional 13-bit break character generat ion / 11-bit break character detection ? selectable transmitter output polarity 4.16.1.2 modes of operation see section 4.16.3, ?functional description ,? for details concerning sci operation in these modes: ? 8 and 9-bit data modes ? loop mode ? single-wire mode 4.16.1.3 block diagram figure 29 shows the transmitter portion of the sci. analog mcu
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 103 figure 29. sci transmitter block diagram figure 30 shows the receiver portion of the sci. h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 ? baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd logic loop control to receive data in to txd tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t* txdir load from sci d tx- brk13
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 104 figure 30. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd rate clock rx interrupt request data recovery divide 16 ? baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rx- lbkde rwuid
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 105 4.16.2 register definition the sci has eight 8-bit registers to control baud rate, select sci options, report sci status, and for transmit/receive data. refer to section 4.6, ?die to die interface - target of this data sheet for the absolute add ress assignments for all sci registers. this section refers to registers and control bits only by their names. 4.16.2.1 sci baud rate regist ers (scibd (hi), scibd (lo)) this pair of registers controls the prescale divisor for sc i baud rate generation. to update the 13-bit baud rate setting [sbr12:sbr0], first write to scibd (hi) to buffer the high half of the new value, and then write to scibd (lo). the working val ue in scibd (hi) does not change until scibd (lo) is written. scibdl is reset to a non-zero value, so after reset the baud ra te generator remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scic2 are written to 1). table 134. sci baud rate register (scibd (hi)) offset (91) 0x40 access: user read/write 76543210 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset00000000 note: 91. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 135. scibd (hi) field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif flag is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif flag is 1. 4:0 sbr[128] baud rate modulo divisor ? the 13 bits in sbr[12:0] are referr ed to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduc e supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 ? br). see also br bits in table 137 . table 136. sci baud rate register (scibdl) offset (92) 0x41 access: user read/write 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset00000100 note: 92. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 137. scibdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ? these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduc e supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 ? br). see also br bits in table 135 .
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 106 4.16.2.2 sci control register 1 (scic1) this read/write register is used to control various optional features of the sci system. table 138. sci control register 1 (scic1) offset (93) 0x42 access: user read/write 76543210 r loops 0 rsrc m 0 ilt pe pt w reset00000000 note: 93. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 139. scic1 fi eld descriptions field description 7 loops loop mode select ? selects between loop back modes and normal 2- pin full-duplex modes. when loops = 1, the transmitter output is internally connect ed to the receiver input. 0 normal operation ? rxd an d txd use separate pins. 1 loop mode or single-wire mode where transmitter outputs are in ternally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 5 rsrc receiver source select ? this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connec ted to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ? start + 8 data bits (lsb first) + stop. 1 receiver and transmitter use 9-bit data characters star t + 8 data bits (lsb first) + 9th data bit + stop. 2 ilt idle line type select ? setting this bit to 1 ensures that t he stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high leve l needed by the idle line detection logic. refer to section 4.16.3.3.2.1, ?idle-line wake-up ? for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable ? enables hardware parity generation and checking. when pa rity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type ? provided parity is enabled (pe = 1), this bit selects even or odd parity. o dd parity means the total number of 1s in the data character, including the parity bit, is odd. even pari ty means the total number of 1s in the data character, includ ing the parity bit, is even. 0 even parity. 1 odd parity.
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 107 4.16.2.3 sci control register 2 (scic2) this register can be read or written at any time. table 140. sci control register 2 (scic2) offset (94) 0x43 access: user read/write 76543210 r tie tcie rie ilie te re rwu sbk w reset00000000 note: 94. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 141. scic2 fi eld descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre flag is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc flag is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf flag is 1. 4 lie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle flag is 1. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 4.16.3.2.1, ?send break and queued idle ? for more details. when te is written to 0, the transmitter keeps control of t he port txd pin until any data, queued idle, or queued break charact er finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ? when the sci receiver is off, the rxd pi n reverts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a gener al-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on.
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 108 4.16.2.4 sci status register 1 (scis1) this register has eight read-only status flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. 1 rwu receiver wake-up control ? this bit can be written to 1 to plac e the sci receiver in a standby state where it waits for automat ic hardware detection of a selected wake-up condition. the wa ke-up condition is either an idle line between messages (wake = 0, idle-line wake-up), or a logic 1 in the most signifi cant data bit in a character (wake = 1, address-mark wake-up). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 4.16.3.3.2, ?receiver wake-up operation ? for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wake-up condition. 0 sbk send break ? writing a 1 and then a 0 to sbk queues a break c haracter in the transmit dat a stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relative to the information curr ently being transmitted, a sec ond break character may be queued before software clears sbk. refer to section 4.16.3.2.1, ?send break and queued idle ? for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. table 142. sci status register 1 (scis1) offset (95) 0x44 access: user read/write 76543210 r tdre tc rdrf idle or nf fe pf w reset11000000 note: 95. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 143. scis1 field descriptions field description 7 tdre transmit data register empty flag ? tdre is set out of rese t and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new characte r in the buffer. to clear tdre, read scis1 with tdre = 1 and then write to the sci data register (scid). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ? tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmission activity complete). tc is cleared automatically by reading scis1 with tc = 1 and then doing one of the following three things: ? write to the sci data register (scid) to transmit new data ? queue a preamble by changing te from 0 to 1 ? queue a break character by writing 1 to sbk in scic2 5 rdrf receive data register full flag ? rdrf becomes set when a ch aracter transfers from the rece ive shifter into the receive data register (scid). to clear rdrf, read scis1 with rdrf = 1 and then read the sci data register (scid). 0 receive data register empty. 1 receive data register full. table 141. scic2 field descriptions (continued) field description
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 109 4.16.2.5 sci status register 2 (scis2) this register has one read-only status flag. 4 idle idle line flag ? idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the st art bit. so if the receive charac ter is all 1s, these bit times and the stop bit time count toward the full character time of logi c high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn? t start counting idle bit times until after the stop bit. so th e stop bit and any logic high bit times at the end of the previous charac ter do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scis1 with idle = 1 and then read the sci data register (scid). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag ? or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scid yet. in this case, the new character (and all associated error information) is lost because there is no room to move it into scid. to clear or, read scis1 with or = 1 and then read the sci data register (scid). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag ? the advanced sampling technique used in the re ceiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if any of these samples di sagrees with the rest of the samples within any bit time i n the frame, the flag nf will be set at the same time as the fl ag rdrf gets set for the character. to clear nf, read scis1 and then read the sci data register (scid). 0 no noise detected. 1 noise detected in the received character in scid. 1 fe framing error flag ? fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a char acter frame. to clear fe, read scis1 with fe = 1 and then read the sci data register (scid). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ? pf is set at the same time as rdrf w hen parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scis1 and then read the sci data register (scid). 0 no parity error. 1 parity error. table 144. sci status register 2 (scis2) offset (96) 0x45 access: user read/write 76543210 r lbkdif rxedgif 0 rxinv(97) rwuid brk13 lbkde raf w reset00000000 note: 96. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 143. scis1 field descriptions (continued) field description
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 110 when using an internal oscillator in a li n system, it is necessary to raise the brea k detection threshold by one bit time. unde r the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times lon g at a slave which is running 14% faster than the master. this woul d trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing e rrors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 4.16.2.6 sci control register 3 (scic3) table 145. scis2 field descriptions field description 7 lbkdif lin break detect interrupt flag ? lbkdif is set when the li n break detect circuitry is enabl ed and a lin break character is detected. lbkdif is cleared by writing a ?1? to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ? rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ?1? to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv (97) receive data inversion ? setting this bit reve rses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect? rwuid controls whether the idle character that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length ? brk13 is used to select a longer transmitted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is tr ansmitted with length of 10 bit times (11 if m = 1) 1 break character is tr ansmitted with length of 13 bit times (14 if m = 1) 1 lbkde lin break detection enable? lbkde is used to select a longer break character detection length. while lbkde is set, framing error (fe) and receive data register full (rdrf) flags are prevented from setting. 0 break character detection enabled. 1 break character detection disabled. note: 97. setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. table 146. sci control register 3 (scic3) offset (98) 0x46 access: user read/write 76543210 rr8 t8 txdir txinv(99) orie neie feie peie w reset00000000 note: 98. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space.
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 111 4.16.2.7 sci data register (scid) this register is actually two separate r egisters. reads return the c ontents of the read-only receiv e data buffer and writes go to the write-only transmit data buffer. reads and writes of this register are also in volved in the automatic flag clearing mechani sms for the sci status flags. table 147. scic3 fi eld descriptions field description 7 r8 ninth data bit for receiver ? when the sci is configured for 9-bi t data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the scid register. when reading 9-bit data, read r8 before reading scid because reading scid completes automatic flag clearing sequences which could allow r8 and scid to be overwritten with new data. 6 t8 ninth data bit for transmitter ? when the sci is configured fo r 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scid regi ster. when writing 9-bit data, the entire 9-bit value is transferre d to the sci shift register after scid is written so t8 should be written (if it needs to change from its previous value) before sci d is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scid is written. 5 txdir txd pin direction in single-wire mo de ? when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines t he direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. 4 txinv (99) transmit data inversion ? setting this bit revers es the polarity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted 3 orie overrun interrupt enable ? this bi t enables the overrun flag (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ? this bit enables the noi se flag (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ? this bit enables the framing error flag (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ? this bit enables the parity error flag (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. note: 99. setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. table 148. sci data register (scid) offset (100) 0x47 access: user read/write 76543210 rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 reset00000000 note: 100. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 112 4.16.3 functional description the sci allows full-duplex, asynchronous, nrz serial commun ication among the mcu and remote devices, including other mcus. the sci comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver operate independently, although they use the same baud rate generator. du ring normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following describes each of the blocks of the sci. 4.16.3.1 baud ra te generation as shown in figure 31 , the clock source for the sci baud rate generator is the d2d clock. figure 31. sci baud rate generation sci communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundaries on every high-to-low trans ition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5 percent for 8-bit data format and about 4.0 percent for 9-bi t data format. although baud rate modulo divider settings do not always produce baud rates that exactly matc h standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 4.16.3.2 transmitter functional description this section describes the overall block di agram for the sci transmitter, as well as specialized functions for sending break an d idle characters. the transmitter block diagram is shown in figure 29 . the transmitter output (txd) idle state defaults to logic high (t xinv = 0 following reset). the tran smitter output is inverted by setting txinv = 1. the transmitter is enabled by setting the te bi t in scic2. this queues a preamble character that is one full character frame of the idle state. the trans mitter then remains idle until data is available in the transmit data buffer. progr ams store data into the transmit data buffer by writing to the sci data register (scid). the central element of the sci transmitter is the transmit shift register that is ei ther 10 or 11 bits long depending on the se tting in the m control bit. for the remainder of this section, we wi ll assume m = 0, selecting the normal 8-bit data mode. in 8-bit dat a mode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmi t data register is transferred to the shif t register (synchronized with the baud rat e clock) and the transmit data register empty (tdre) status flag is set to indicate another character may be written to the transmit dat a buffer at scid. if no new character is waiting in the tran smit data buffer after a stop bit is shif ted out the txd pin, t he transmitter sets th e transmit complete flag and enters an idle mode, with txd hi gh, waiting for more characters to transmit. writing 0 to te does not immediately release the pin to be a gener al-purpose i/o pin. any transmit activity that is in progress must first be completed. this includes data characters in progress, queued idle characters, and queued break characters. 4.16.3.2.1 send break and queued idle the sbk control bit in scic2 is used to send break characters wh ich were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer bre ak of 13 bit times can be enabled by setting brk13 = 1. normally, a prog ram would wait for tdre to bec ome set to indicate the last character of a message has move d to the transmit shifter, then write 1 and then writ e 0 to the sbk bit. this action queues a br eak character to be sent as soon as the shifter is available. if sbk is still 1 when the queued break moves into the shifter sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 d2d baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 113 (synchronized to the baud rate clock), an additional break char acter is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wake-up is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become se t to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the te bit. this action queues an idle characte r to be sent as soon as the s hifter is available. as long as the character in the shifter does not finish while te = 0, the sci transmitter never actually releases c ontrol of the txd pin. if there is a possibility of the shifter finishing while te = 0, set t he general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affected by the brk13 and m bits as shown below. 4.16.3.3 receiver f unctional description in this section, the receiver block diagram ( figure 30 ) is used as a guide for the overall re ceiver functional description. next, the data sampling technique used to reconstruct receiver data is descr ibed in more detail. finally, two variations of the receiver wake-up function are explained. the receiver input is inverted by setting rxinv = 1. the receiver is enabled by setting the re bit in scic2. character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb first), and a stop bit of logic 1. for information about 9-bi t data mode, refer to section ?, ?8 and 9-bit data modes .? for the remainder of this discussion, we assume the sci is configured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provid ed the receive data register is not already full, the data cha racter is transferred to the receive data register and the receive data register full (rdrf) status flag is set. if rdrf was already set indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. b ecause the sci receiver is double-buffered, the program has one full char acter time after rdrf is set before the data in the receive d ata buffer must be read to avoid a receiver overrun. when a program detects that the receive data register is full ( rdrf = 1), it gets the data from the receive data register by read ing scid. the rdrf flag is cleared automatically by a 2-step sequen ce which is normally satisfied in the course of the user?s program that handles receive data. refer to section 4.16.3.4, ?inte rrupts and status flags ? for more details about flag clearing. 4.16.3.3.1 data sampling technique the sci receiver uses a 16 ? baud rate clock for sampling. the receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. the 16 ? baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a falling edge is located, three more samples are taken at rt 3, rt5, and rt7 to make sure this was a real start bit and not merely noise. if at least two of these three samples are 0, the receiver assumes it is synch ronized to a receive character. the receiver then samples each bit time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is in terpreted to be that of the majo rity of the samples taken during the bit time. in the case of th e start bit, the bit is assumed to be 0 if at least two of the samples at rt 3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (inc luding the start and stop bits) in a character frame fails to agre e with the logic level for that bit, the noise flag (nf) will be set when the received character is transferred to the receive da ta buffer. the falling edge detection logic continuously looks for fa lling edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of t he receiver in the presence of noise or mismatched baud rates. i t does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. in the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. table 149. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 114 in the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cle ared. the receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if fe is still set. 4.16.3.3.2 receiver wake-up operation receiver wake-up is a hardware mechanism that allows an sci rece iver to ignore the characters in a message that is intended for a different sci receiver. in such a s ystem, all receivers evaluate the first character(s) of each message, and as soon as t hey determine the message is intended for a different receiver, they wr ite logic 1 to the receiver wake up (rwu) control bit in sci c2. when rwu bit is set, the status flags associated with the receiv er (with the exception of the id le bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. at the end of a message, or at the beginning of the next message, all re ceivers automatically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message. 4.16.3.3.2.1 idle-line wake-up when wake = 0, the receiver is configured for idle-line wake-up. in this mode, rwu is cleared automatically when the receiver detects a full character time of the idle-line level. the m co ntrol bit selects 8-bit or 9-bit data mode that determines how ma ny bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). when rwu is one and rwuid is zero, the idle condition that wa kes up the receiver does not set the idle flag. the receiver wakes up and waits for the first data character of the next message which will set the rdrf fl ag and generate an interrupt if enabled. when rwuid is one, any idle condition sets the idle fl ag and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit selects one of two ways to dete ct an idle line. when ilt = 0, the idle bit counter starts af ter the start bit so the stop bit and any logic 1s at the end of a charac ter count toward the full charac ter time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so th e idle detection is not affected by the data in the last char acter of the previous message. 4.16.3.3.2.2 address-mark wake-up when wake = 1, the receiver is configured for address-mark wa ke-up. in this mode, rwu is cleared automatically when the receiver detects a logic 1 in the most significant bit of a rece ived character (eighth bit in m = 0 mode and ninth bit in m = 1 mod e). address-mark wake-up allows messages to contain idle characte rs but requires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf flag. in this case the character with the msb set is re ceived even though the receiver was sleepi ng during most of this character time. 4.16.3.4 interrupts and status flags the sci system has three separate interrupt vectors to reduce the amount of softwa re needed to isolat e the cause of the interrupt. one interrupt vector is associated with the transmitter for tdre and tc events. another interrupt vector is associat ed with the receiver for rdrf, idle, rxedgif and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separate ly masked by local interrupt enable masks. the flags can still b e polled by software when the local masks are cleared to disable generation of hardware interrupt requests. the sci transmitter has two status flags that optionally can gene rate hardware interrupt requests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scid. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. tran smit complete (tc) indicates that the transmitter is finished transmitting all data, preamble, and break charac ters and is idle with txd at the inactive lev el. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrup t enable (tcie) bit is set, a hardware interr upt will be requested whenever tc = 1. inste ad of hardware interrupts, software pollin g may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receive data register is full ( rdrf = 1), it gets the data from the receive data register by read ing scid. the rdrf flag is cleared by reading scis1 while rdrf = 1 and then reading scid. when polling is used, this sequence is natur ally satisfied in the normal course of th e user program. if hardware interrupts are used, scis1 must be read in the interrupt se rvice routine (isr). normally, this is d one in the isr anyway to check for receive errors, so the sequence is automatically satisfied. the idle status flag includes logic that prevents it from getting set repeatedly w hen the rxd line remains idle for an extended period of time. idle is cleared by reading scis1 while idle = 1 and then reading scid. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf.
serial communication interface (s08sciv4) mm912_634 advance information, rev. 4.0 freescale semiconductor 115 if the associated error was detected in the received character t hat caused rdrf to be set, the error flags ? noise flag (nf), framing error (fe), and parity error flag (pf) ? get set at th e same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is ready to be transferred from the rece ive shifter to the receive data buffer, th e overrun (or) flag gets set instead the data along wi th any associated nf, fe, or pf condition is lost. at any time, an active edge on the rxd serial data input pin causes the rxedgif flag to set. the rxedgif flag is cleared by writing a ?1? to it. this function does depend on the receiver being enabled (re = 1). 4.16.3.5 additional sci functions the following sections describe additional sci functions. 4.16.3.5.1 8- and 9- bit data modes the sci system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the m control bit in scic1 . in 9-bit mode, there is a ninth data bit to the left of the msb of the sci data register. for the transmit data buffer, this bi t is stored in t8 in scic3. for the receiver, the ninth bit is held in r8 in scic3. for coherent writes to the tran smit data buffer, write to the t8 bit before writing to scid. if the bit value to be transmitted as the ni nth bit of a new character is the same as for the previous character, it is not nec essary to write to t8 again. when data is transfe rred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferr ed from scid to the shifter. 9-bit data mode typically is used in conjunction with parity to allo w eight bits of data plus the parity in the ninth bit. or i t is used with address-mark wake-up so the ninth data bi t can serve as the wake-up bit. in custom protocols, the ninth bit can also serve as a software-controlled marker. 4.16.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci register data is lost and must be re-initialized upon recovery from these two stop modes. no sci module registers are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode, but not in stop2. an active edge on the receive inp ut brings the cpu out of stop3 mode if th e interrupt is not masked (rxedgie = 1). note that because the clocks are halted, the sci module will resu me operation upon exit from stop (only in stop3 mode). softwar e should ensure stop mode is not entered while there is a charac ter being transmitted out of or received into the sci module. 4.16.3.5.3 loop mode when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is sometimes used to check software, independent of co nnections in the external system, to help isolate system problems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general purpose port i/o pin. 4.16.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). single-wire mode is used to implement a half-duplex serial conne ction. the receiver is interna lly connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general purpose port i/o pin. in single-wire mode, the txdir bit in scic3 controls the directi on of serial data on the txd pi n. when txdir = 0, the txd pin is an input to the sci receiver and the transmitter is temporarily disconnected from the txd pin so an external device can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wire mode, the interna l loop back connection from the transmitter to the receiver causes the receiver to receive characte rs that are sent out by the transmitter.
high voltage inputs - lx mm912_634 advance information, rev. 4.0 freescale semiconductor 116 4.17 high voltage inputs - lx six high voltage capable inputs are im plemented with the following features: ? digital input capable ? analog input capable with selectable voltage divider. ? wake-up capable during low power mode. see section 4.9, ?wake-up / cyclic sense . when used as analog inputs to sense voltages outside the modu le a series resistor must be used on the used input. when a lx input is not selected in the analog multiplexer, the voltage divi der is disconnected from that input. when a lx input is select ed in the analog multiplexer, it will be disconnected in low power mode if configured as wake-up input. unused lx pins are recommended to be connected to gnd to improve emc behavior. 4.17.1 register definition 4.17.1.1 lx status register (lxr) 4.17.1.2 lx control register (lxcr) table 150. lx status register (lxr) offset (101) 0x08 access: user read 76543210 r0 0 l5l4l3l2l1l0 w note: 101. offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 151. lxr - register field descriptions field description l[5-0] lx status register - current digital state of the lx input table 152. lx control register (lxcr) offset (102) 0x09 access: user read/write 76543210 r0 0 l5ds l4ds l3ds l2ds l1ds l0ds w reset00000000 note: 102. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 153. lxcr - register field descriptions field description 5-0 l[5-0]ds analog input divider ratio selection - lx 0 - 2 (typ.) 1 - 7.2 (typ) analog mcu
general purpose i/o - ptb[0?2] mm912_634 advance information, rev. 4.0 freescale semiconductor 117 4.18 general purpose i/o - ptb[0?2] the three multipurpose i/o pins can be configured to operate as documented in the table below. the alternate function of ptb2, ptb1 and ptb0 can be configur ed by selecting the function in the corresponding module (e.g. timer). the selection with the highest priority will ta ke effect when more than one function is selected. 4.18.1 digital i/o functionality all three pins act as standard digital inputs / outputs with selectable pull-up resistor. 4.18.2 alternative sci / lin functionality for alternative serial configuration and for debug and certificat ion purpose, ptb0 and ptb1 can be configured to connect to the internal lin and / or sci signals (rxd and txd). figure 32 shows the 4 available configurations. figure 32. alternative sci / lin functionality 4.18.3 alternative pwm functionality as an alternative routing for the pwm channel (0 or 1) output, the portb 2 (ptb2) can be configured to output one of the two pwm channels defined in the section 4.14, ?pwm control module (pwm8b2c) . the selection and output enable can be configured in the port b conf iguration register 2 (ptbc2). table 154. general purpos e i/o - operating modes priority function ptb2 ptb1 ptb0 chp/pg 1 (h) 2.5 v analog input ad2 ad1 ad0 4.20/133 2 timer input capture / output compare timch2 timch1 timch0 4.19/120 3 lin / sci - rx / tx (ptb0?1) or pwm (ptb2) pwm tx rx 4.15/100 4 (l) 5.0 v input output ptb2 ptb1 ptb0 current analog mcu serial communication interface (sci) lin physical layer interface 4 channel timer module ptb0/ad0/tim0ch0/rx ptb1/ad1/tim0ch1/tx ptb2/ad2/tim0ch2/pwm lin tim0ch3 rx tx rx tx serial communication interface (sci) lin physical layer interface 4 channel timer module ptb0/ad0/tim0ch0/rx ptb1/ad1/tim0ch1/tx ptb2/ad2/tim0ch2/pwm lin tim0ch3 rx tx rx tx serial communication interface (sci) lin physical layer interface 4 channel timer module ptb0/ad0/tim0ch0/rx ptb1/ad1/tim0ch1/tx ptb2/ad2/tim0ch2/pwm lin tim0ch3 rx tx rx tx serial communication interface (sci) lin physical layer interface 4 channel timer module ptb0/ad0/tim0ch0/rx ptb1/ad1/tim0ch1/tx ptb2/ad2/tim0ch2/pwm lin tim0ch3 rx tx rx tx mode 0 (default) mode 1 (external sci) mode 2 (external lin) mode 3 (observe)
general purpose i/o - ptb[0?2] mm912_634 advance information, rev. 4.0 freescale semiconductor 118 4.18.4 register definition 4.18.4.1 port b configuration register 1 (ptbc1) note the pull-up resistor is not active once the port is configured as an output. 4.18.4.2 port b configuration register 2 (ptbc2) table 155. port b configuration register 1 (ptbc1) offset (103) 0x20 access: user read/write 76543210 r0 pueb2 pueb1 pueb0 0 ddrb2 ddrb1 ddrb0 w reset00000000 note: 103. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 156. ptbc1 - register field descriptions field description 6-4 pueb[2-0] pull-up enable port b[2?0] 0 - pull-up disabled on ptbx pin. 1- pull-up enabled on ptbx pin. 2-0 ddrb[2-0] data direction port b[2?0] 0 - ptbx configured as input. 1 - ptbx configured as output. table 157. port b configuration register 2 (ptbc2) offset (104) 0x21 access: user read/write 76543210 r0000 pwmcs pwmen sermod w reset00000000 note: 104. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space.
general purpose i/o - ptb[0?2] mm912_634 advance information, rev. 4.0 freescale semiconductor 119 4.18.4.3 port b data register (ptb) table 158. ptbc2 - register field descriptions field description 3 pwmcs pwm channel select ptb2. see section 4.14, ?pwm control module (pwm8b2c) . 0 - pwm channel 0 selected as pwm channel for ptb2 1 - pwm channel 1 selected as pwm channel for ptb2 2 pwmen pwm enable for ptb2. see section 4.14, ?pwm control module (pwm8b2c) . 0 - pwm disabled on ptb2 1 - pwm enabled on ptb2 (channel as selected with pwmcs) 1-0 sermod serial mode select for ptb0 and ptb1. see figure 32 for details. 00 - mode 0, sci internally connect ed the lin physical layer interface. ptb0 and ptb1 are digital i/os 01 - mode 1, sci connected to ptb0 and ptb1 (external sci mode) 10 - mode 2, lin physical layer interface connected to ptb0 and ptb1 (external lin mode) 11 - mode 3, sci internally connected the lin physical layer interface and ptb0 and ptb1 are connected both as outputs (observe mode) table 159. port b data register (ptb) offset (105) 0x22 access: user read/write 76543210 r00000 ptb2 ptb1 ptb0 w reset00000000 note: 105. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 160. ptb - register field descriptions field description 2-0 ptb[2-0] port b general purpose input/output data ? data register if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered and synchronized pin input state is read.
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 120 4.19 basic timer modul e - tim (tim16b4c) 4.19.1 introduction 4.19.1.1 overview the basic timer consists of a 16-bit, software-programmabl e counter driven by a seven-stage programmable prescaler. this timer can be used for many purposes, including input wa veform measurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. this timer contains 4 complete input captur e/output compare channels [ioc 3:2]. the in put capture function is used to detect a selected transition edge and record the time. the output compar e function is used for generating output signals or for timer software delays. a full access for the counter registers or the input capture/output compare registers should take place in 16bit word access. accessing high byte and low byte separately for all of these regist ers may not yield the same result as accessing them in one word. 4.19.1.2 features the tim16b4c includes these distinctive features: ? four input capture/output compare channels. ? clock prescaler ? 16-bit counter 4.19.1.3 modes of operation the tim16b4c is only active during normal mode. 4.19.1.4 block diagram figure 33. timer block diagram for more information see the respective functional descriptions see section 4.19.4, ?functional description of this chapter. analog mcu prescaler 16-bit counter ioc1 ioc0 ioc2 ioc3 timer overflow interrupt registers d2d clock input capture output compare input capture output compare input capture output compare input capture output compare channel 0 channel 1 channel 2 channel 3 timer channel 0 interrupt timer channel 3 interrupt
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 121 4.19.2 signal description 4.19.2.1 overview the tim16b4c module is internally connected to the ptb ( ioc0, ioc1, ioc2) and to the rx signal as specified in section 4.18, ?general purpose i/o - ptb[0?2] (ioc3). 4.19.2.2 detailed signal descriptions 4.19.2.2.1 ioc3 ? input capture and output compare channel 3 this pin serves as input captur e or output compare for channel 3 and is internally connected to the rx signal as specified in section 4.18.2, ?alternative sci / lin functionality . note since the rx signal is only available as an i nput, using the output compare feature for this channel would have no effect. 4.19.2.2.2 ioc2 ? input capture and output compare channel 2 this pin serves as an input capture or output compare for channel 2 and can be routed to the ptb2 general purpose i/o. 4.19.2.2.3 ioc1 ? input capture and output compare channel 1 this pin serves as an input capture or output compare for channel 1 and can be routed to the ptb1 general purpose i/o. 4.19.2.2.4 ioc0 ? input capture and output compare channel 0 this pin serves as an input capture or output compare for channel 0 and can be routed to the ptb0 general purpose i/o. note for the description of interrupts see section 4.19.6, ?interrupts . 4.19.3 memory map and registers 4.19.3.1 overview this section provides a detailed description of all memory and registers. 4.19.3.2 module memory map the memory map for the tim16b4c module is given below in table 161 . table 161. module memory map offset (106) use access 0xc0 timer input capture/output compare select (tios) read/write 0xc1 timer compare force register (cforc) read/write (107) 0xc2 output compare 3 mask register (oc3m) read/write 0xc3 output compare 3 data register (oc3d) read/write 0xc4 timer count register (tcnt(hi)) read/write (108) 0xc5 timer count register (tcnt(lo)) read/write (107) 0xc6 timer system control register 1 (tscr1) read/write 0xc7 timer toggle overflow register (ttov) read/write 0xc8 timer control register 1 (tctl1) read/write 0xc9 timer control register 2 (tctl2) read/write 0xca timer interrupt enable register (tie) read/write 0xcb timer system control register 2 (tscr2) read/write 0xcc main timer interrupt flag 1 (tflg1) read/write
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 122 4.19.3.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. 4.19.3.3.1 timer input capture/output compare select (tios) 4.19.3.3.2 timer compare force register (cforc) 0xcd main timer interrupt flag 2 (tflg2) read/write 0xce timer input capture/output compare register 0 (tc0(hi)) read/write (109) 0xcf timer input capture/output compare register 0 (tc0(lo)) read/write (108) 0xd0 timer input capture/output compare register 1 (tc1(hi)) read/write (108) 0xd1 timer input capture/output compare register 1 (tc1(lo)) read/write (108) 0xd2 timer input capture/output compare register 2 (tc2(hi)) read/write (108) 0xd3 timer input capture/output compare register 2 (tc2(lo)) read/write (108) 0xd4 timer input capture/output compare register 3 (tc3(hi)) read/write (108) note: 106. offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 107. always read $00. 108. only writable in special modes. (refer to soc guide for different modes). 109. write to these registers have no meaning or effect during input capture. table 162. timer input capture/output compare select (tios) offset (110) 0xc0 access: user read/write 76543210 r0000 ios3 ios2 ios1 ios0 w reset00000000 note: 110. offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. table 163. tios - register field descriptions field description 3-0 ios[3-0] input capture or output compare channel configuration 0 - the corresponding channel acts as an input capture. 1 - the corresponding channel acts as an output compare. table 164. timer compare force register (cforc) offset (111) 0xc1 access: user read/write 76543210 r00000000 w foc3 foc2 foc1 foc0 reset00000000 note: 111. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 161. module memory map offset (106) use access
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 123 a write to this register with the corresponding (foc 3:0) data bit(s) set causes the action pr ogrammed for output compare on channel ?n? to occur immediately.the action taken is the same as if a successful comparison ha d just taken place with the tcn register except the interrupt flag does not get set. note a successful channel 3 output compare overrides any channel 2:0 compares. if forced output compare on any channel occurs at the sa me time as the successful output compare then forced output compare action will take precedence and interrupt flag will not get set. 4.19.3.3.3 output compare 3 mask register (oc3m) setting the oc3mn (n ranges from 0 to 2) will set the correspondi ng port to be an output port when the corresponding tiosn (n ranges from 0 to 2) bit is set to be an output compare. note a successful channel 3 output compare ov errides any channel 2:0 compares. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. 4.19.3.3.4 output compare 3 data register (oc3d) table 165. cforc - regist er field descriptions field description 3-0 foc[3-0] force output compare action for channel 3-0 0 - force output compare action disabled. input capture or output compare channel configuration 1 - force output compare action enabled table 166. output compare 3 mask register (oc3m) offset (112) 0xc2 access: user read/write 76543210 r0000 oc3m3 oc3m2 oc3m1 oc3m0 w reset00000000 note: 112. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 167. oc3m - register field descriptions field description 3-0 oc3m[3-0] output compare 3 mask "n" channel bit 0 - does not set the corresponding port to be an output port 1 - sets the corresponding port to be an output port when this corresponding tios bit is set to be an output compare table 168. output compare 3 data register (oc3d) offset (113) 0xc3 access: user read/write 76543210 r 0 0 0 0 oc3d3 oc3d2 oc3d1 oc3d0 w reset00000000 note: 113. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 124 note a channel 3 output compare will cause bits in th e output compare 3 data register to transfer to the timer port data register if the corresp onding output compare 3 mask register bits are set. 4.19.3.3.5 timer count register (tcnt) note the 16-bit main timer is an up counter. a full access for the counter register should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. the period of the first count after a write to the tcnt registers may be a different lengt h because the write is not synchronized with the prescaler clock. 4.19.3.3.6 timer system co ntrol register 1 (tscr1) table 169. oc3d - register field descriptions field description 3-0 oc3d[3-0] output compare 3 data for channel "n" table 170. timer count register (tcnt) offset (114) 0xc4, 0xc5 access: user read( anytime)/write (special mode) 15 14 13 12 11 10 9 8 r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w reset00000000 76543210 r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w reset00000000 note: 114. offset related to 0x0200 for blocki ng access and 0x300 for non blocking access within the global address space. table 171. tcnt - register field descriptions field description 15-0 tcnt[15-0] 16 bit timer count register table 172. timer system control register 1 (tscr1) offset (115) 0xc6 access: user read/write 76543210 r ten 00 tffca 0000 w reset00000000 note: 115. offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space.
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 125 4.19.3.3.7 timer toggle on overflow register 1 (ttov) note tovn toggles output compare pin on overflow . this feature only takes effect when the corresponding channel is configured for an output compare mode. wh en set, an overflow toggle on the output compare pin takes prece dence over forced output compare events. 4.19.3.3.8 timer control register 1 (tctl1) table 173. tscr1 - register field descriptions field description 7 ten timer enable 1 = enables the timer. 0 = disables the timer. (used fo r reducing power consumption). 4 tffca timer fast flag clear all 1 = for tflg1 register, a read from an input capture or a write to the output compare channel [tc 3:0] causes the corresponding channel flag, cnf, to be cleared.for tflg2 regi ster, any access to the tc nt register clears the tof flag. any access to the pacnt registers clears the paovf and paif bits in the paflg register. this has the advantage of eliminating software overhead in a separate cl ear sequence. extra care is required to avoid accidental flag clearing due to unintended accesses. 0 = allows the timer flag clearing. table 174. timer toggle on overflow register 1 (ttov) offset (116) 0xc7 access: user read/write 76543210 r0000 tov3 tov2 tov1 tov0 w reset00000000 note: 116. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 175. ttov - register field descriptions field description 3-0 tov[3-0] toggle on overflow bits 1 = toggle output compare pin on overflow feature enabled. 0 = toggle output compare pin on overflow feature disabled. table 176. timer contro l register 1 (tctl1) offset (117) 0xc8 access: user read/write 76543210 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w reset00000000 note: 117. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access with in the global address space.
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 126 note these four pairs of control bits are encoded to specify the output action to be taken as a result of a successful output compare on "n " channel. when either omn or oln, the pin associated with the corresponding channel becomes an output tied to its ioc. to enable output action by the omn and oln bits on a ti mer port, the corresponding bit in oc3m should be cleared. 4.19.3.3.9 timer control register 2 (tctl2) these four pairs of control bits configur e the input capture edge detector circuits. table 177. tctl1 - register field descriptions field description 7,5,3,1 omn output mode bit 6,4,2,0 oln output level bit table 178. compare result output action omn oln action 0 0 timer disconnected from output pin logic 0 1 toggle ocn output line 1 0 clear ocn output line to zero 1 1 set ocn output line to one table 179. timer contro l register 2 (tctl2) offset (118) 0xc9 access: user read/write 76543210 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w reset00000000 note: 118. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access with in the global address space. table 180. tctl2 - register field descriptions field description edgnb,edgna input capture edge control table 181. edge detector circuit configuration edgnb edgna configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling)
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 127 4.19.3.3.10 timer interrupt enable register (tie) 4.19.3.3.11 timer system co ntrol register 2 (tscr2) note this mode of operation is similar to an up-counting modulus counter. if register tc3 = $0000 and tcre = 1, the timer counter register (tcnt) will stay at $0000 continuously. if register tc3 = $ffff and tcre = 1, tof will not be set when the timer counter register (tcnt) is reset from $ffff to $0000. the newly selected prescale factor will not take effect until the next synchronized edge, where all prescale counter stages equal zero. table 182. timer interrupt enable register (tie) offset (119) 0xca access: user read/write 76543210 r0000 c3i c2i c1i c0i w reset00000000 note: 119. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 183. tie - register field descriptions field description 3-0 c[3-0]i input capture/output compare interrupt enable. 1 = enables corresponding interrupt flag (cnf of tfl g1 register) to cause a hardware interrupt 0 = disables corresponding interrupt flag (cnf of tflg1 register) from causing a hardware interrupt table 184. timer system control register 2 (tscr2) offset (120) 0xcb access: user read/write 76543210 r toi 000 tcre pr2 pr1 pr0 w reset00000000 note: 120. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 185. tie - register field descriptions field description 7 toi timer overflow interrupt enable 1 = hardware interrupt requested when tof flag set in tflg2 register. 0 = hardware interrupt request inhibited. 3 tcre tcre ? timer counter reset enable 1 = enables timer counter reset by a successful output compare on channel 3 0 = inhibits timer counter reset and counter continues to run. 3-0 pr[2:0] timer prescaler select these three bits select the frequency of the timer pres caler clock derived from the bus clock as shown in table 186 .
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 128 4.19.3.3.12 main timer interrupt flag 1 (tflg1) note these flags are set when an input capture or output compare event occurs. flag set on a particular channel is cleared by writing a one to that corresponding cnf bit. writing a zero to cnf bit has no effect on its status. when tffca bit in tscr register is set, a read from an input capture or a write into an output compare channel will cause the corresponding channel flag cnf to be cleared. 4.19.3.3.13 main timer interrupt flag 2 (tflg2) table 186. timer clock selection pr2 pr1 pr0 timer clock 0 0 0 d2d clock / 1 0 0 1 d2d clock / 2 0 1 0 d2d clock / 4 0 1 1 d2d clock / 8 1 0 0 d2d clock / 16 1 0 1 d2d clock / 32 1 1 0 d2d clock / 64 1 1 1 d2d clock / 128 table 187. main timer in terrupt flag 1 (tflg1) offset (121) 0xcc access: user read/write 76543210 r0 0 0 0 c3fc2fc1fc0f w reset00000000 note: 121. offset related to 0x0200 for blocking access and 0x300 for non blocking access wi thin the global address space. table 188. tflg1 - regist er field descriptions field description 3-0 c[3:0]f input capture/output compare channel flag. 1 = input capture or output compare event occurred 0 = no event (input capture or output compare event) occurred. table 189. main timer in terrupt flag 2 (tflg2) offset (112) 0xcd access: user read/write 76543210 r tof 0000000 w reset00000000 note: 122. offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space.
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 129 note the tflg2 register indicates when an interrup t has occurred. writing a one to the tof bit will clear it. any access to tcnt will clear tof bit of tflg2 register if the tffca bit in tscr register is set. 4.19.3.3.14 timer input capture/outp ut compare registers (tc3 - tc0) table 190. tflg2 - regist er field descriptions field description 7 tof timer overflow flag 1 = indicates that an interrupt has occurred (set when 16- bit free-running timer counter overflows from $ffff to $0000) 0 = flag indicates an interrupt has not occurred. table 191. timer input capture/output compare register 0 (tc0) offset (123) 0xce, 0xcf access: user read(anytime)/write (special mode) 15 14 13 12 11 10 9 8 r tc0_15 tc0_14 tc0_13 tc0_12 tc0_11 tc0_10 tc0_9 tc0_8 w reset00000000 76543210 r tc0_7 tc0_6 tc0_5 tc0_4 tc0_3 tc0_2 tc0_1 tc0_0 w reset00000000 note: 123. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 192. timer input capture/output compare register 1(tc1) offset (124) 0xd0, 0xd1 access: user read( anytime)/write (special mode) 15 14 13 12 11 10 9 8 r tc1_15 tc1_14 tc1_13 tc1_12 tc1_11 tc1_10 tc1_9 tc1_8 w reset00000000 76543210 r tc1_7 tc1_6 tc1_5 tc1_4 tc1_3 tc1_2 tc1_1 tc1_0 w reset00000000 note: 124. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access with in the global address space.
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 130 note tread anytime. write anytime for output compar e function. writes to these registers have no effect during input capture. depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter wh en a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. read/write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 4.19.4 functional description 4.19.4.1 general this section provides a complete functional description of the timer tim16b4c block. refer to the detailed timer block diagram in figure 34 as necessary. table 193. timer input capture/output compare register 2(tc2) offset (125) 0xd2, 0xd3 access: user read(anytime)/write (special mode) 15 14 13 12 11 10 9 8 r tc2_15 tc2_14 tc2_13 tc2_12 tc2_11 tc2_10 tc2_9 tc2_8 w reset00000000 76543210 r tc2_7 tc2_6 tc2_5 tc2_4 tc2_3 tc2_2 tc2_1 tc2_0 w reset00000000 note: 125. offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 194. timer input capture/output compare register 3(tc3) offset (126) 0xd4, 0xd5 access: user read( anytime)/write (special mode) 15 14 13 12 11 10 9 8 r tc3_15 tc3_14 tc3_13 tc3_12 tc3_11 tc3_10 tc3_9 tc3_8 w reset00000000 76543210 r tc3_7 tc3_6 tc3_5 tc3_4 tc3_3 tc3_2 tc3_1 tc3_0 w reset00000000 note: 126. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access with in the global address space. table 195. tcn - register field descriptions field description 15-0 tcn[15-0] 16 timer input capture/output compare registers
basic timer module - tim (tim16b4c) mm912_634 advance information, rev. 4.0 freescale semiconductor 131 figure 34. detailed timer block diagram 4.19.4.2 prescaler the prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64, or 128. the prescaler select bits , pr[2:0], select the prescaler divisor. pr[2:0] are in the timer system control register 2 (tscr2). 4.19.4.3 input capture clearing the i/o (input/output) select bit, iosn, configures channel n as an input capture channel. the input capture function captures the time at which an external event occurs. when an ac tive edge occurs on the pin of an input capture channel, the timer transfers the value in the timer count er into the timer channel registers, tcn. the minimum pulse width for the input capture input is greater than two bus clocks. an input capture on channel n sets the cnf flag. the cni bit enables the cnf flag to generate interrupt requests. 4.19.4.4 output compare setting the i/o select bit, iosn, configures channel n as an output compare channel. the output compare function can generate a periodic pulse with a programmable polarity, duration, and fre quency. when the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. an output compare on channel n set s the cnf flag. the cni bit enables the cnf flag to generate interrupt requests. the output mode and level bits, omn and oln, select set, clear, toggle on output compare. clearing both omn and oln disconnects the pin from the output logic. prescaler channel 0 ioc0 pin 16-bit counter logic pr[2:1:0] tc0 16-bit comparator tcnt(hi):tcnt(lo) interrupt logic tof toi c0f edge detect cxf channel3 tc3 16-bit comparator c3f ioc3 pin logic edge detect om:ol0 tov0 om:ol3 tov3 edg3a edg3b edg0b tcre clear counter cxi ch.3 compare ch.3 capture ioc0 pin ioc3 pin te ch. 0 compare ch. 0 capture pa input edg0a channel 3 output compare ioc0 ioc3 d2d clock tof c0f c3f
mm912_634 advance information, rev. 4.0 freescale semiconductor 132 setting a force output compare bit, focn, causes an output compare on channel n. a forced output compare does not set the channel flag. a successful output compare on channel 3 overrides output comp ares on all other output comp are channels. the output compare 3 mask register masks the bits in the output compare 3 data regi ster. the timer counter reset ena ble bit, tcre, enables channel 3 output compares to reset the timer count er. a channel 3 output compare can reset the timer counter even if the ioc3 pin is being used as the pulse accumulator input. writing to the timer port bit of an output compare pin does not affect the pin state. the value written is stored in an interna l latch. when the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. 4.19.5 resets 4.19.5.1 general the reset state of each individual bit is lis ted within the register description section 4.19.3, ?memory map and registers? , which details the registers and their bit-fields. 4.19.6 interrupts 4.19.6.1 general this section describes interrupts or iginated by the tim16b4c block. table 196 lists the interrupts generated by the tim16b4c to communicate with the mcu. 4.19.6.2 description of interrupt operation the tim16b4c uses a total of 5 interrupt vectors. the interrupt vector offsets and interrupt numbers are chip dependent. more information on interrupt vector offsets and interrupt numbers can be found in the section 4.7, ?interrupts 4.19.6.2.1 channel [3:0] interrupt these active high outputs are asserted by the module to reque st a timer channel 3?0 interrupt, following an input capture or output compare event on these c hannels [3-0]. for the interrupt to be asserted on a specific channel, the enable, cni bit of ti e register should be set. t hese interrupts are serviced by the system controller. 4.19.6.2.2 timer overfl ow interrupt (tof) this active high output will be asserted by the module to req uest a timer overflow interrupt, following the timer counter overf low when the overflow enable bit (toi) bit of tflg2 register is set. th is interrupt is serviced by the system controller. table 196. tim16b4c interrupts interrupt offset vector priority source description c[3:0]f - - - timer channel 3-0 activ e high timer channel interrupts 3-0 tof - - - timer overflow timer overflow interrupt
analog digital converter - adc mm912_634 advance information, rev. 4.0 freescale semiconductor 133 4.20 analog digital converter - adc 4.20.1 introduction 4.20.1.1 overview in order to sample the mm912_634 analog die analog sources, a 10-bit resolution successive approximation analog to digital converter has been implemented. controlled by the a/d control logic (adc wrapper), t he analog digital converter allows fast and high precision conversions. figure 35. analog digita l converter block diagram 4.20.1.2 features ? 10-bit resolution ? 13 s (typ.), 10-bit single sample + conversion time ? external adc2p5 pin with over-current protection to filter the analog reference voltage ? total error (te) of 5 lsb without offset calibration active ? integrated selectable offset compensation ? 14 + 1 analog channels (ad0?8; isense, tsense and vsense, vs1sense, bandgap, plus calibration channel) ? sequence- and continuous conversion mode with irq for sequence complete indication ? dedicated result register for each channel 4.20.2 modes of operation the analog digital converter module is active only in normal mode; it is disabled in sleep and stop mode. 4.20.3 external signal description this section lists and describes the signals that do connect off-chip. table 197 shows all the pins and their functions that are controlled by the analog digital converter module. analog mcu a d a/d control logic (adc wrapper) d2dclk analog multiplexer startconv, clka2d, samplea2d_n data registers dataa2d ad_ref (adc2p5, agnd)
analog digital converter - adc mm912_634 advance information, rev. 4.0 freescale semiconductor 134 4.20.4 memory map and register definition 4.20.4.1 module memory map table 198 shows the register map of the analog digital converter mo dule. all register addresses given are referenced to the d2d interface offset. table 197. adc - pin func tions and priorities pin name pin function & priority i/o description pin function after reset agnd analog ground - analog ground connection - adc2p5 analog regulator - analog digital converter regulator filter terminal. a capacitor c adc2p5 is required for operation. - table 198. analog digital con verter module - memory map register / offset (127) bit 7 6 5 4 3 2 1 bit 0 0x80 acr r scie cce oce adcrst 0 ps2 ps1 ps0 w 0x81 asr r scf 2p5clf 0 0 ccnt3 ccnt2 ccnt1 ccnt0 w 0x82 accr (hi) r ch15 ch14 0 ch12 ch11 ch10 ch9 ch8 w 0x83 accr (lo) r ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w 0x84 accsr (hi) r cc15 cc14 0cc12 cc11 cc10 cc9 cc8 w 0x85 accsr (lo) r cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 w 0x86 adr0 (hi) r adr0[9:2] w 0x87 adr0 (lo) r adr0[1:0] w 0x88 adr1 (hi) r adr1[9:2] w 0x89 adr1 (lo) r adr1[1:0] w 0x8a adr2 (hi) r adr2[9:2] w 0x8b adr2 (lo) r adr2[1:0] w 0x8c adr3 (hi) r adr3[9:2] w 0x8d adr3 (lo) r adr3[1:0] w 0x8e adr4 (hi) r adr4[9:2] w
mm912_634 advance information, rev. 4.0 freescale semiconductor 135 0x8f adr4 (lo) r adr4[1:0] w 0x90 adr5 (hi) r adr5[9:2] w 0x91 adr5 (lo) r adr5[1:0] w 0x92 adr6 (hi) r adr6[9:2] w 0x93 adr6 (lo) r adr6[1:0] w 0x94 adr7 (hi) r adr7[9:2] w 0x95 adr7 (lo) r adr7[1:0] w 0x96 adr8 (hi) r adr8[9:2] w 0x97 adr8 (lo) r adr8[1:0] w 0x98 adr9 (hi) r adr9[9:2] w 0x99 adr9 (lo) r adr9[1:0] w 0x9a adr10 (hi) r adr10[9:2] w 0x9b adr10 (lo) r adr10[1:0] w 0x9c adr11 (hi) r adr11[9:2] w 0x9d adr11 (lo) r adr11[1:0] w 0x9e adr12 (hi) r adr12[9:2] w 0x9f adr12 (lo) r adr12[1:0] w 0xa0 reserved r w 0xa1 reserved r w 0xa2 adr14 (hi) r adr14[9:2] w 0xa3 adr14 (lo) r adr14[1:0] w table 198. analog digital con verter module - memory map register / offset (127) bit 7 6 5 4 3 2 1 bit 0
mm912_634 advance information, rev. 4.0 freescale semiconductor 136 4.20.4.2 register definition 4.20.4.2.1 adc config register (acr) 0xa4 adr15 (hi) r adr15[9:2] w 0xa5 adr15 (lo) r adr15[1:0] w note: 127. offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 199. adc config register (acr) offset (128) 0x80 access: user read/write 76543210 r scie cce oce adcrst 0 ps2 ps1 ps0 w reset00000000 note: 128. offset related to 0x0200 for blocking access and 0x3 00 for non blocking access wi thin the global address space. table 200. acr - register field descriptions field description 7 - scie sequence complete interrupt enable 0 - sequence complete interrupt disabled 1 - sequence complete interrupt enabled 6 - cce continuous conversion enable 0 - continuous conversion disabled 1 - continuous conversion enabled 5 - oce offset compensation enable 0 - offset compensation disabled 1 - offset compensation enabled. this feature requires t he ch15 bit in the adc conversion control register (accr) to be set for all conversions 4 - adcrst analog digital converter reset 0 - analog digital converter in normal operation 1 - analog digital converter in reset mode. all adc registers will reset to initial values. the bit has to be cleared to allow adc operation 2-0 ps2?0 adc clock prescaler select (d2dclk to adcclk divider) 000 - 10 001 - 8 010 - 6 011 - 4 100 - 2 101 - 1 110 - 1 111 - 1 table 198. analog digital con verter module - memory map register / offset (127) bit 7 6 5 4 3 2 1 bit 0
mm912_634 advance information, rev. 4.0 freescale semiconductor 137 note adcrst is strongly recommended to be set during d2d clock frequency changes. 4.20.4.2.2 adc status register (asr) 4.20.4.2.3 adc conv ersion control register (accr) table 201. adc status register (asr) offset (129) 0x81 access: user read/write 76543210 r scf 2p5clf 0 0 ccnt3 ccnt2 ccnt1 ccnt0 w reset00001111 note: 129. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access with in the global address space. table 202. acr - register field descriptions field description 7 - scf sequence complete flag. reading the adc st atus register (asr) will clear the flag. 6 - 2p5clf adc reference voltage current limitation flag 3-0 ccnt3?0 conversion counter status. the content of ccnt reflects t he current channel in conversion and the conversion of ccnt-1 being complete. the conversion order is ch15, ch0, ch1,..., ch14. table 203. adc conversion control register (accr) offset (130) 0x82 (0x82 and 0x83 for 8-bit access) access: user read/write 1514131211109876543210 r ch15 ch14 0 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset0000000000000000 note: 130. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 204. accr - register field descriptions field description 15-0 chx channel select - if 1, the selected channel is included into the sequence. writing accr will stop the current sequence and restart. writing accr=0 will stop the conversion, all ccx flags will be cleared when accr is written.conversion will start after write. 16-bit write operation recommended, writing 8-bit: only writing the high byte wi ll start the conversion with channel 15, if selected. write to the low byte will not start a conversion. measure individual channels by writing a sequence of one channel. channel 15 needs to be selected in order to have the offset compensation functional.
mm912_634 advance information, rev. 4.0 freescale semiconductor 138 4.20.4.2.4 adc conversi on complete status register (accsr) 4.20.4.2.5 adc data resu lt register x (adrx) 4.20.5 functional description 4.20.5.1 analog channel definitions the following analog channels are routed to the analog multiplexer: table 205. adc conversi on complete status register (accsr) offset (131) 0x84 (0x84 and 0x85 for 8-bit access) access: user read 1514131211109876543210 r cc15 cc14 0cc12 cc11 cc10 cc9 cc8 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 w reset0000000000000000 note: 131. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 206. accsr - regist er field descriptions field description 15-0 ccx conversion complete flag - indicates the conversion being complete for channel x. read operation only.16-bit read recommended. 8-bit read will return the current status, no latching will be performed. table 207. adc data result register x (adrx) offset (132) 0x86+x (0x86 and 0x87 for 8-bit access) access: user read 1514131211109876543210 r adrx 0 0 0000 w reset0000000000000000 note: 132. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 208. adrx - register field descriptions field description 15-6 adrx adc - channel x left adjusted result register. reading the regi ster will clear the corresponding ccx register in the accsr register. 16-bit read recommended. 8-bit read: reading the low byte will latch the high byte for the next read, reading the high byte will clear the cc flag. table 209. analog channels channel description 0 ad0 - ptb0 analog input ad0 1 ad1 - ptb1 analog input ad1 2 ad2 - ptb2 analog input ad2 3 ad3 - l0 analog input ad3 4 ad4 - l1 analog input ad4 5 ad5 - l2 analog input ad5 6 ad6 - l3 analog input ad6
mm912_634 advance information, rev. 4.0 freescale semiconductor 139 4.20.5.2 automatic of fset compensation to eliminate the analog digital converter offset, an automatic compensation is implemented. the compensation is based on a calibrated voltage reference connected to adc channel 15. the re ference trim is accomplished by the correct ctrx register content. see section 4.26, ?mm912_634 - analog die trimming . the reference is factory trimmed to 8 lsb. to activate the offset compensation feature, the oce bit in th e adc config register (acr) has to be set, and the ch15 has to be enabled when starting a new conversion, by writing to the adc conversion control register (accr). the compensation will work with single and sequence conversion. figure 36. automatic offset compensation 4.20.5.3 conversion timing the conversion timing is based on the adcclk generated by the adc prescaler (ps) out of the d2dclk signal. the prescaler needs to be configured to have the adcclk match the specified f adc clock limits. 7 ad7 - l4 analog input ad7 8 ad8 - l5 analog input ad8 9 current sense isense 10 voltage sense vsense 11 temperature sense tsense 12 vs1 sense vs1sense 13 not implemented n.i. 14 bandgap (133) bandgap 15 calibration reference cal note: 133. internal ?bg1p25sleep? reference. table 209. analog channels channel description oce ? offset compensation enable = 1 mcu ? ifr (4c..4f) => ctr0..3 accr ? adc conversion control register ch15=1 + chx = 1 read adrx after scf is set sample ch15 offset is calculated as difference between result and 8 lsb sample chx adjust chx result by calculated offset ch15 is a trimmed reference of 8 lsb (requires ctrx) internal all x
mm912_634 advance information, rev. 4.0 freescale semiconductor 140 a conversion is divi ded into the follo wing 27+ clock cycles: ? 9 cycle sampling time ? 18 cycle remaining conversion time ? a worst case (only channel 14) of 15 clock cycles to count up to the selected channel (15, 0, 1,....14) ? 4 cycles between two channels example 1. single conver sion channe l 10 (vsense) 12c (count up to ch10) + 9c (sample) + 18c (conversion) = 39 cycles from start to end of conversion. example 2. sequence of channel 10 (vsense) + channel 15 (offset compensation) 1c (count) + 9c (sample ch15) + 18c (conversion ch15) + 4c (i n between) + 0c (count further to ch10 is performed while converting ch15) + 9c (sample) + 18c (conversion) = 59 cycles from start to end of both conversions.
current sense module - isense mm912_634 advance information, rev. 4.0 freescale semiconductor 141 4.21 current sense module - isense the current sense module is implem ented to amplify the voltage drop ac ross an external shunt resistor to measure the actual application current using the internal analog digital converter channel 9. typical application is the motor current in a window lift control module . figure 37. current sense module with external filter option the implementation is based on a switched capacitor solution to eliminate unwanted offset.to fit several application scenarios, eight different gain setting are implemented. 4.21.1 register definition 4.21.1.1 current sense register (csr) table 210. current sense register (csr) offset (134) 0x3c access: user read/write 76543210 r cse 000 ccd csgs w reset00000000 note: 134. offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. analog mcu in q c imot p1 p1 p2 filt c filt r vin vout adc shunt r filt r in q c g ? 2 c g ? 2 vin ? isenseh isensel in q c imot p1 p1 p2 filt c filt r vin vout adc shunt r filt r in q c g ? 2 c g ? 2 vin ? isenseh isensel
current sense module - isense mm912_634 advance information, rev. 4.0 freescale semiconductor 142 table 211. csr - register field descriptions field description 7 cse current sense enable bit 0 - current sense module disabled 1 - current sense module enabled 3 ccd input filter charge compensation disable bit (135) 0 - enabled 1 - disabled 2-0 csgs current sense gain select - selects the amplification gain for the current sense module 000 - 7 (typ.) 001 - 9 (typ.) 010 - 10 (typ.) 011 - 12 (typ.) 100 - 14 (typ.) 101 - 18 (typ.) 110 - 24 (typ.) 111 - 36 (typ.) note: 135. this feature should be used when implementi ng an external filter to the current sense isensex inputs. in principal an inter nal charge compensation is activated in synch with t he conversion to avoid the sample capacitors to be discharged by the external filter.
temperature sensor - tsense mm912_634 advance information, rev. 4.0 freescale semiconductor 143 4.22 temperature sensor - tsense to be able to measure the current mm912_634 analog die chip temperature, the tsen se feature is implemented. a constant temperature related gain of tsg can be routed to the internal analog digital converter (channel 11). figure 38. tsense - graph refer to the section 4.20, ?analog digital converter - adc for details on the channel selection and analog measurement. note due to internal capacitor charging, temperature measurements are valid 200 ms (max) after system power up and wake-up. analog mcu 2.5 2.0 1.5 1.0 0.5 v -50c 0c 50c 100c 150c t 1,984v 150c typ. 0,15v -50c typ.
supply voltage sense - vsense mm912_634 advance information, rev. 4.0 freescale semiconductor 144 4.23 supply voltage sense - vsense the reverse battery protected vsense pin has been implem ented to allow a direct measurement of the battery level voltage. bypassing the device vsup capacitor and external reverse battery diode will detect under-voltage conditions without delay. a series resistor is required to protect the mm912_634 analog die from fast transients. figure 39. vsense module the voltage present on the vsense pin can be routed via an internal divider to the internal analog digital converter or issue a n interrupt (lbi) to alert the mcu. for the interrupt based alert, see section 4.5, ?power supply . for vsense measurement using the internal adc see section 4.20, ?analog digital converter - adc . 4.24 internal supply voltage sense - vs1sense in addition to the vsense module, the internal vs1 supply ca n be routed to the analog digital converter as well. see section 4.20, ?analog digital converter - adc for details on the acquisition. i figure 40. vs1sense module 4.25 internal bandgap refere nce voltage sense - bandgap the internal reference bandgap voltage ?bg1p25sleep? is gener ated fully independent from the analog digital converter reference voltages. measuring (136) the ?bg1p25sleep? reference through the adc-ch14 al lows should return a conversion result within adch14 under normal conditions. any result outside the range would indicate faulty behavior of either the adc chain or the 2p5sleep bandgap circuity. note: 136. the maximum allowed sample frequency for channel 14 is limit ed to fch14. increasing the sample frequency above can result i n unwanted turn off of the ls drivers due to a false vreg over-voltage. analog mcu vs1 vsense vs2 prescaler ratio vsense mux ch11 adc r vsense lbi vs1 vsense vs2 mux adc r vsense lvi prescaler ratio vs1 ch12 analog mcu analog mcu
mm912_634 - analog die trimming mm912_634 advance information, rev. 4.0 freescale semiconductor 145 4.26 mm912_634 - analog die trimming a trimming option is implemented to increase some device parameter accuracy. as the mm912_634 analog die is exclusively combined with a flash- mcu, the required tr imming values can be calculat ed during the final test of the device, and stored to a fixed posit ion in the flash memory. during start- up of the system, the trimming values have to be copied into the mm912_634 analog die trimming registers. the trimming registers will maintain their content du ring low power mode, reset will set the default value. 4.26.1 memory map and register definition 4.26.1.1 module memory map there are four trimming registers implemen ted (ctr0?ctr3), with ctr2 being reserved for future use. the following table shows the registers used. at system startup, the trimming informati on have to be copied from the mcu ifr flas h location to the co rresponding mm912_634 analog die trimming registers. the following table shows the register correlation. note two word (16-bit) transfers including ctr2 are recommended at system startup. the ifr register has to be enabled for reading ( section 4.29.3.2.3, ?mmc control register (mmcctl1) ) note to trim the bg1p25sleep there is two steps: step 1: first choose the right trim step by adjusting slpbgtr [2:0] with slpbgtre=1, slpbg_lock bit has to stay at 0. step 2: once the trim value is know n, correct slpbgtr[2 :0], slpbgtre and slpbg_lock bits have to be set at the same ti me to apply and lock the trim. once the trim is locked, no other trim on the parameter is possible. table 212. mm912_634 analog die trimming registers offset name 7 6 5 4 3 2 1 0 0xf0 ctr0 r lintre lintr wdctre ctr0_4 ctr0_3 wdctr2 wdctr1 wdctr0 trimming reg 0 w 0xf1 ctr1 r bgtre ctr1_6 bgtrimu p bgtrimd n ireftre ireftr2 ireftr1 ireftr0 trimming reg 1 w 0xf2 ctr2 r 0 0 0 slpbgtr e slpbg_loc k slpbgtr 2 slpbgtr 1 slpbgtr 0 trimming reg 2 w 0xf3 ctr3 r offctr e offctr 2 offctr1 offctr0 ctr3_e ctr3_2 ctr3_1 ctr3_0 trimming reg 3 w note: 137. offset related to 0x0200 for bloc king access and 0x300 for non blocking access within t he global address space. table 213. mm912_634 - mcu vs. analog die trimming register correlation name mcu ifr address analog offset (138) ctr0 0x4c 0xf0 ctr1 0x4d 0xf1 ctr2 0x4e 0xf2 ctr3 0x4f 0xf3 note: 138. offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space. analog mcu
mm912_634 - analog die trimming mm912_634 advance information, rev. 4.0 freescale semiconductor 146 4.26.1.2 register descriptions 4.26.1.2.1 trimming register 0 (ctr0) 4.26.1.2.2 trimming register 1 (ctr1) table 214. trimming register 0 (ctr0) offset (139) 0xf0 access: user read/write 76543210 r lintre lintr wdctre ctr0_4 ctr0_3 wdctr2 wdctr1 wdctr0 w reset00000000 note: 139. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 215. ctr0 - register field descriptions field description 7 lintre lin trim enable 0 - no trim can be done 1- trim can be done by setting lintr bit 6 lintr lin trim bit 0 - default slope 1 - adjust the slope 5 wdctre watchdog trim enable 0 - no trim can be done 1 - trim can be done by setting wdctr[2:0] bits 4 ctr0_4 spare trim bit 4 3 ctr0_3 spare trim bit 3 2-0 wdctr2?0 watchdog clock trim (trim effect to the 100 khz watch dog base clock) 000: 0% 001: +5% 010: +10% 011: +15% 100: -20% 101: -15% 110: -10% 111: -5% table 216. trimming register 1 (ctr1) offset (140) 0xf1 access: user read/write 76543210 r bgtre ctr1_6 bgtrimup bgtrimdn ireftre ireftr2 ireftr1 ireftr0 w reset00000000 note: 140. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space.
mm912_634 - analog die trimming mm912_634 advance information, rev. 4.0 freescale semiconductor 147 4.26.1.2.3 trimming register 2 (ctr2) table 217. ctr1 - register field descriptions field description 7 bgtre bandgap trim enable 0 - no trim can be done 1 - trim can be done by setting bgtrimup and bgtrimdn bits 6 ctr1_6 spare trim bit 5 bgtrimup bandgap trim up bit 0 - default slope 1 - increase bandgap slope 4 bgtrimdn bandgap trim down bit 0 - default slope 1 - decrease bandgap slope 3 ireftre iref trim enable bit 0 - no trim can be done 1 - trim can be done by setting ireftr[2:0] bits 2-0 ireftr2?0 iref trim - this trim is used to adjust the internal zero tc current reference 000: 0% 001: +7.6% 010: +16.43% 011: +26.83% 100: -8.54% 101: -15.75% 110: -21.79% 111: 0% table 218. trimming register 2 (ctr2) offset (141) 0xf2 access: user read/write 765 4 3 210 r0 0 0 slpbgtre slpbg_lock slpbgtr2 slpbgtr1 slpbgtr0 w reset000 0 0 000 note: 141. offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
mm912_634 - analog die trimming mm912_634 advance information, rev. 4.0 freescale semiconductor 148 4.26.1.2.4 trimming register 3 (ctr3) table 219. ctr2 - register field descriptions field description 4 slpbgtre sleep bandgap trim enable 0 no trim can be done 1 trim lock can be done by setting slpbgtr[2:0] bits and slpbg_lock bit 3 slpbg_lock bg1p25sleep trim lock bit 2-0 slpbgtr2?0 bg1p25sleep trim - this trim is used to adjust the intern al sleep mode 1.25 v bandgap used as a reference for the vdd and vddx over-voltage detection. 000: -12.2% (default) 001: -8.2% 010: -4.2% 011: 0% 100: +4.2% 101: +8.3% 110: +12.5% 111: -12.2% (default) table 220. trimming register 3 (ctr3) offset (142) 0xf3 access: user read/write 76543210 r offctre offctr2 offctr1 offctr0 ctr3_e ctr3_2 ctr3_1 ctr3_0 w reset00000000 note: 142. offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 221. ctr3 - register field descriptions field description 7 offctre adc offset compensation voltage trim enable bit 0 - no trim can be done 1 - trim can be done by setting offctr[2:0] bits 6-4 offctr2?0 adcoffc trim - this trim is used to adjust the internal adc offset compensation voltage 000: 0% 001: +7.98% 010: +15.97% 011: +23.95% 100: -23.95% 101: -15.97% 110: -7.98% 111: 0% 3 ctr3_e spare trim enable bit 2 ctr3_2 spare trim bit 2
mm912_634 advance information, rev. 4.0 freescale semiconductor 149 1 ctr3_1 spare trim bit 1 0 ctr3_0 spare trim bit 0 table 221. ctr3 - register field descriptions field description
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 150 4.27 mm912_634 - mcu die overview 4.27.1 introduction the mc9s12i64 micro controller implem ented in the mm912_634 is designed as counter part to an analog die, and is not being offered as a standalone mcu. the mc9s12i64 device contains a s12 cent ral processing unit (cpu), offers 64kb of flash memory and 6.0 kb of system sram, up to eight general purpose i/os, an on-chip oscillator and clock multiplier, one serial peripheral interface (spi), an interrupt module and debug capabilities via the on-chip debu g module (dbg) in combination with the background debug mode (bdm) interface. additionally there is a die-to-die initiator (d2di) which represents the communication interface to the compan ion (analog) die. 4.27.2 features this section describes the key features of the mc9s12i64 micro controller unit. 4.27.2.1 chip-level features on-chip modules available within the fa mily include the following features: ? s12 cpu core (cpu12_v1) ? kbyte on-chip flash with ecc ? 4.0 kbyte on-chip data flash with ecc ? 6.0 kbyte on-chip sram ? phase locked loop (ipll) frequency multiplier with internal filter ? 4?16 mhz amplitude controlled pierce oscillator ? 1.0 mhz internal rc oscillator ? one serial peripheral interface (spi) module ? on-chip voltage regulator (vreg) for regulation of input supply and all internal voltages ? die to die initiator (d2di) 4.27.3 module features the following sections provide more details of the modules implemented on the mc9s12i64. 4.27.3.1 s12 16-bit centra l processor unit (cpu) s12 cpu is a high-speed 16-bit processing unit: ? full 16-bit data paths supports efficient arithmetic operation and high-speed math execution ? includes many single-byte instructions. this allows much more efficient use of rom space. ? extensive set of indexed addr essing capabilit ies, including: ? using the stack pointer as an indexing register in all indexed operations ? using the program counter as an indexing regi ster in all but auto in crement/decrement mode ? accumulator offsets using a, b, or d accumulators ? automatic index pre-decrement, pre-increment, post-decrement, and post-increment (by ?8 to +8) 4.27.3.2 on-chip flash with ecc on-chip flash memory on the mc9s12i64 features the following: ? kbyte of program flash memory ? 32 data bits plus 7 syndrome ecc (error correction code) bits allow single bit error correction and double fault detection ? erase sector size 512 bytes ? automated program and erase algorithm ? user margin level setting for reads ? protection scheme to prevent accidental program or erase analog mcu
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 151 ? 4.0 kbyte data flash memory ? 16 data bits plus 6 syndrome ecc (error correction code) bits allow single bit error correction and double-bit error detection ? erase sector size 256 bytes ? automated program and erase algorithm ? user margin level setting for reads 4.27.3.3 on-chip sram 6.0 kbytes of general-purpose ram 4.27.3.4 main external oscillator (xosc) loop controlled pierce oscillator using a 4.0 mhz to 16 mhz crystal or resonator ? current gain control on amplitude output ? signal with low harmonic distortion ? low power ? good noise immunity ? eliminates need for external current limiting resistor ? transconductance sized for optimum start-up margin for typical crystals 4.27.3.5 internal rc oscillator (irc) trimmable internal reference clock. 4.27.3.6 intern al phase-locked loop (ipll) phase-locked loop clock frequency multiplier ? no external components required ? reference divider and multiplier allow large variety of clock rates ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? configurable option to spread spectrum for reduced emc radiation (frequency modulation) ? reference clock sources: ? external 4.0 to 16 mhz resonator/crystal (xosc) ? internal 1.0 mhz rc oscillator (irc) 4.27.3.7 system integrity support ? power-on reset (por) ? system reset generation ? illegal address detection with reset ? low-voltage detection with interrupt or reset ? real time interrupt (rti) ? computer operating properly (cop) watchdog ? configurable as window cop for enhanced failure detection ? initialized out of reset using option bits located in flash memory ? clock monitor supervising the co rrect function of the oscillator 4.27.3.8 serial peripheral interface module (spi) ? configurable 8 or 16-bit data size ? full-duplex or single-wire bidirectional ? double-buffered transmit and receive ? master or slave mode ? msb-first or lsb-first shifting ? serial clock phase and polarity options
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 152 4.27.3.9 on-chip voltage regulator (vreg) ? linear voltage regulator with bandgap reference ? low-voltage detect (lvd) with low-voltage interrupt (lvi) ? power-on reset (por) circuit ? low-voltage reset (lvr) 4.27.3.10 background debug (bdm) ? non-intrusive memory access commands ? supports in-circuit programming of on-chip nonvolatile memory 4.27.3.11 debugger (dbg) ? trace buffer with depth of 64 entries ? three comparators (a, b and c) ? comparator a compares the full address bus and full 16-bit data bus ? exact address or address range comparisons ? two types of comparator matches ? tagged: this matches just before a s pecific instruction begins execution ? force: this is valid on the first instruction boundary after a match occurs ? four trace modes ? four stage state sequencer 4.27.3.12 die to die initiator (d2di) ? up to 2.0 mbyte/s data rate ? configurable 4-bit or 8-bit wide data path figure 4.27.4 shows mc9s12i64 cpu and bdm local addres s translation to the global memory map. it indicates also the location of the internal resources in the memory map. the whole 256 k gl obal memory space is visible through the p-flash window located in the 64 k local memory map located at 0x8000 - 0xbfff using the ppage register.
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 153 figure 41. mc9s12i128 global memory map 0x3_ffff ppage cpu and bdm local memory map global memory map 0xffff 0xc000 0x8000 p-flash window 0x3_4000 0x3_8000 0x3_c000 0x0_4000 0x0000 0x4000 0x0400 d-flash 4k bytes ram 6k bytes unpaged p-flash 0p0 p1 p2 p3 0 0 0 0x1400 0x0_0000 ram 6k p-flash 0x0_8000 nvm resources 0x0_2800 0x3_0000 unpaged p-flash (ppage 0x0c) (ppage 0x0d) (ppage 0x0e) (ppage 0x0f) (ppages (ppage 0x01) (ppage 0x00) 0x0_4400 d-flash 0x0_5400 0x2800 page 0x0f unpaged p-flash page 0x0d unpaged p-flash page 0x0c registers registers 4* 16k pages nvm resources unpaged p-flash unpaged p-flash 0x08-0x0b) (ppages 0x02-0x07) unimplemented unimplemented 0x2_0000
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 154 4.27.4 part id assignments the part id is located in two 8-bit registers partidh and pa rtidl (addresses 0x001a and 0x001b). the read-only value is a unique part id for each revision of the chip. table 222 shows the assigned part id number and mask set number. the version id in ta b l e 2 2 2 is a word located in a flash information row. the version id number indicates a specific version of internal nvm controller. 4.27.5 system clock description for the system clock descr iption please refer to 4.38, ?s12 clock, reset and power management unit (s12cpmu) ? . 4.27.6 modes of operation the mcu can operate in different modes. these are described in section 4.27.6.1, ?chi p configuration summary ? . the mcu can operate in different power modes to facilita te power saving when fu ll system performance is not required. these are described in section 4.27.6.2, ?low power operation ? . some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. 4.27.6.1 chip conf iguration summary the different modes and the security state of the mcu affect the debug features (enabled or disabled). the operating mode out of reset is determined by the state of the modc signal during reset (see table 223 ). the modc bit in the mode register shows the cu rrent operating mode and provides limited mode s witching during operation. the state of the modc signal is latched into this bit on the rising edge of reset . 4.27.6.1.1 normal single-chip mode this mode is intended for normal device operation. the opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). the pr ocessor program is executed from internal memory. 4.27.6.1.2 special single-chip mode this mode is used for debugging single-chip operation, boot-st rapping, or security related operations. the background debug module bdm is active in this mode. the cpu executes a monito r program located in an on-chip rom. bdm firmware waits for additional serial commands through the bkgd pin. 4.27.6.2 low power operation the mm912_634 has two static low-power modes pseudo stop a nd stop mode. for a detailed description refer to s12cpmu section. 4.27.7 security the mcu security mechanism prevents unauthorized access to the flash memory. refer to 4.33, ?security (s12x9secv2) ? , section 4.31.4.1, ?security ? , and section 4.40.5, ?security ? . table 222. assigned part id numbers device mask set number part id (143) version id mc9s12i64 0n53a 0x38c0 0x0000 note: 143. the coding is as follows: bit 15-12: major family identifier bit 11-6: minor family identifier bit 5-4: major mask set revisi on number including fab transfers bit 3-0: minor ? non full ? mask set revision table 223. chip modes chip modes modc normal single chip 1 special single chip 0
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 155 4.27.8 resets and interrupts consult the s12 cpu manual and the s12sint section for information on exception processing. 4.27.8.1 resets table 224 lists all reset sources and t he vector locations. resets are explained in detail in the 4.38, ?s12 clock, reset and power management unit (s12cpmu) ? . 4.27.8.2 interru pt vectors table 225 lists all interrupt sources and vectors in the def ault order of priority. the interrupt module (see 4.30, ?interrupt module (s12sintv1) ? ) provides an interrupt vector base r egister (ivbr) to relocate the vectors. table 224. reset sources and vector locations vector address reset source ccr mask local enable $fffe power-on reset (por) none none $fffe low voltage reset (lvr) none none $fffe external pin reset none none $fffe illegal address reset none none $fffc clock monitor reset none osce bit in cpmuosc register $fffa cop watchdog reset none cr[2:0] in cpmucop register table 225. interrupt vector locations (sheet 1 of 2) vector address (144) interrupt source ccr mask local enable wake-up from stop vector base + $f8 unimplemented instruction trap none none - vector base+ $f6 swi none none - vector base+ $f4 d2di error interrupt x bit none yes vector base+ $f2 d2di external error interrupt i bit d2dctl (d2die) yes vector base+ $f0 rti timeout interrupt i bit cpmuint (rtie) vector base + $ee to vector base + $da reserved vector base + $d8 spi i bit spicr1 (spie, sptie) no vector base + $d6 to vector base + $ca reserved vector base + $c8 oscillator status interrupt i bit cpmuint (oscie) no vector base + $c6 pll lock interrupt i bit cpmuint (lockie) no vector base + $c4 to vector base + $bc reserved vector base + $ba flash error i bit fercnfg (sfdie, dfdie) no vector base + $b8 flash command i bit fcnfg (ccie) no vector base + $b6 to vector base + $8c reserved vector base + $8a low-voltage interrupt (lvi) i bit cpmuctrl (lvie) no vector base + $88 to vector base + $82 reserved
mm912_634 - mcu die overview mm912_634 advance information, rev. 4.0 freescale semiconductor 156 4.27.8.3 effects of reset when a reset occurs, mcu registers and control bits are initializ ed. refer to the respective blo ck sections for register reset states. on each reset, the flash module executes a reset sequence to load flash c onfiguration registers. 4.27.8.3.1 flash configuration reset sequence phase on each reset, the flash module will hold cpu activity while loading flash module registers from the flash memory. if double faults are detected in the reset phase, flash module protection and security may be active on leaving reset. this is explained in more detail in the flash module section 4.40.6, ?initialization ? . 4.27.8.3.2 reset while flash command active if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed. 4.27.8.3.3 i/o pins refer to the pim section for reset confi gurations of all peripheral module ports. 4.27.8.3.4 memory the ram arrays are not initialized out of reset. 4.27.9 cop configuration the cop time-out rate bits cr[ 2:0] and the wcop bit in the cpmucop register at address 0x003c are loaded from the flash register fopt. see table 226 and table 227 for coding. the fopt register is loaded fr om the flash configuration field byte at global address 0x3_ff0e during the reset sequence. vector base + $80 spurious interrupt ? none - note: 144. 16 bits vector address based table 226. initial cop rate configuration nv[2:0] in fopt register cr[2:0] in copctl register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 table 227. initial wcop configuration nv[3] in fopt register wcop in copctl register 10 01 table 225. interrupt vector locations (sheet 2 of 2) vector address (144) interrupt source ccr mask local enable wake-up from stop
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 157 4.28 port integrati on module (s12ipimv1) 4.28.1 introduction the port integration module (pim) establishes the inte rface between the mc9s12i64 peripheral modules spi and die-to-die interface module (d2di) to the i/o pins of the mcu. all port a and port e pins support general purpose i/o functional ity if not in use with other fu nctions. the pim controls the s ignal prioritization and multiplexing on shared pins. figure 42. block diagram 4.28.1.1 features ? 8-pin port a associated with the spi module ? 2-pin port c used as d2di clock output and d2di interrupt input ? 8-pin port d used as 8 or 4 bit data i/o for the d2di module ? 2-pin port e associated with the cpmu osc module ? gpio function shared on port a, e pins ? pull-down devices on pc1 and pd7-0 if used as d2di inputs ? reduced drive capability on pc0 and pd7-0 on per pin basis the port integration module includes these distinctive registers: ? data registers for ports a, e when used as general-purpose i/o ? data direction registers for ports a, e when used as general-purpose i/o ? port input register on ports a and e ? reduced drive register on port c and d 4.28.2 memory map and register definition this section provides a detailed description of all port integration module registers. analog mcu d2dclk d2dint d2ddat0 d2ddat1 d2di die-to-die if pa3 pa0 pa1 pa2 pa4 pa5 miso mosi sck ss spi synchronous serial if d2ddat2 d2ddat3 d2ddat4 d2ddat5 d2ddat6 d2ddat7 ddra port integration module porta pa6 pa7 pd3 pd0 pd1 pd2 pd4 pd5 pd6 pd7 pc0 pc1 elements pe0 pe1 ddre porte cpmu osc extal xtal
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 158 4.28.2.1 memory map 4.28.2.2 port a data register (porta) register name bit 7654321bit 0 0x0000 porta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w 0x0001 portb r000000 pe1 pe0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddrb r000000 ddre1 ddre0 w 0x0004- 0x0009 reserved r00000000 w 0x000c pucr r0 bkpue 0000 pdpee 0 w 0x000d rdriv r0000 rdpd rdpc 00 w 0x0120 ptia r ptia7 ptia6 ptia5 ptia4 ptia3 ptia2 ptia1 ptia0 w 0x0121 ptib r000000ptie1ptie0 w 0x0122- 0x17f reserved r00000000 w = unimplemented or reserved figure 43. port a data register (porta) address 0x0000 access: user read/write (145) 76543210 r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w spi function ????sssckmosimiso reset00000000 note: 145. read: anytime. write: anytime.
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 159 4.28.2.3 port e data register (porte) pim table 228. porta register field descriptions field description 7?4 pa port a general purpose input/output data ?data registerin output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered and synchronized pin input state is read. 3 pa port a general purpose input/output data ?data register, spi ss input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. ? the spi function takes precedence over t he general purpose i/o function if enabled. 2 pa port a general purpose input/output data ?data register, spi sck input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. ? the spi function takes precedence over t he general purpose i/o function if enabled. 1 pa port a general purpose input/output data ?data register, spi mosi input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. ? the spi function takes precedence over t he general purpose i/o function if enabled. 0 pa port a general purpose input/output data ?data register, spi miso input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. ? the spi function takes precedence over t he general purpose i/o function if enabled. table 229. port e data register (porte) address 0x0001 access: user read/write (146) 76543210 r 0 0 0 000 pe1 pe0 w cpmu osc function ??????xtalextal reset00000000 note: 146. read: anytime. write: anytime.
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 160 4.28.2.4 port a data direction register (ddra) 4.28.2.5 port e data direction register (ddre) table 230. porte regist er field descriptions field description 1 pe port e general purpose input/output data ?data register, cpmu osc xtal signal when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. ? the cpmu osc function takes precedence ov er the general purpose i/o function if enabled. 0 pe port e general purpose input/output data ?data register, cpmu osc extal signal when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. ? the cpmu osc function takes precedence ov er the general purpose i/o function if enabled. figure 44. port a data direction register (ddra) address 0x0002 access: user read/write (147) 76543210 r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w reset00000000 note: 147. read: anytime. write: anytime. table 231. ddra register field descriptions field description 7?4 ddra port a data direction ? this bit determines whether the associated pin is an input or output. 1 associated pin is configured as output. 0 associated pin is configured as input. 3?0 ddra port a data direction ? this bit determines whether the associated pin is an input or output. depending on the configuration of the enabled spi the i/o state will be forced to input or output. in this case the data direct ion bits will not change. 1 associated pin is configured as output. 0 associated pin is configured as input. figure 45. port e data direction register (ddre) address 0x0003 access: user read/write (148) 76543210 r 0 0 0 000 ddre1 ddre0 w reset00000000 note: 148. read: anytime. write: anytime.
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 161 4.28.2.6 pim reserved registers these registers are reserved for factory te sting of the pim module. writing to thes e addresses can alter the module functionali ty. 4.28.2.7 pull contro l register (pucr) table 232. ddre register field descriptions field description 1?0 ddre port e data direction ? this bit determines whether the associated pin is an input or output. the enabled cpmu osc function connects the associated pins directly to the oscillator modul e. in this case the data direction bits will not change. 1 associated pin is configured as output. 0 associated pin is configured as input. table 233. pim reserved registers address 0x0004-0x0009 access: user read (149) 76543210 r00000000 w reset00000000 = unimplemented or reserved note: 149. read: always reads 0x00 write: not allowed table 234. pull control register (pucr) address 0x0124 access: user read/write (150) 76543210 r 0 bkpue 0 0 0 0 pdpee 0 w reset01000010 note: 150. read: anytime. write: anytime. table 235. pucr register field descriptions field description 6 bkpue bkgd pin pull-up enable?enabl e pull-up devices on bkgd pin. this bit configures whether a pull-up device is activated, if the pin is used as input. this bit has no effect if the pin is used as output. out of reset the pull-up device is enabled. 1 pull-up device enabled. 0 pull-up device disabled. 1 pdpee pull-down port e enable?enable pull-down devices on all port e i nput pins. this bit configures whether pull-down devices are activated, if the pins are used as inputs . this bit has no effect if the pins are used as outputs. out of reset the pull-down d evices are enabled. if the cpmu osc function is active the pull-down devices are disabled. in th is case the register bit will not chan ge. 1 pull-down devices enabled. 0 pull-down devices disabled.
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 162 4.28.2.8 reduced drive register (rdriv) 4.28.2.9 port a input register (ptia) table 236. reduced drive register (rdriv) address 0x000d access: user read/write (151) 76543210 r 0 0 0 0 rdpd rdpc 00 w reset00000000 note: 151. read: anytime. write: anytime. table 237. rdriv register field descriptions field description 3 rdpd port d reduced drive ? select reduced drive for output pins. this bit configures the drive strengt h of output pins as either full or reduced. if a pin is used as input this bit has no effect. 1 reduced drive selected (1/5 of the full drive strength) 0 full drive strength enabled 2 rdpc port c reduced drive ? select reduced drive for d2dclk output pin. this bit configures the drive strength of d2dclk output pin as either full or reduced. 1 reduced drive selected (1/5 of the full drive strength) 0 full drive strength enabled table 238. port a input register (ptia) address 0x0120 access: user read (152) 76543210 r ptia7 ptia6 ptia5 ptia4 ptia3 ptia2 ptia1 ptia0 w reset (153) uuuuuuuu note: 152. read: anytime. write: unimplemented. writing to this register has no effect. 153. u = unaffected by reset table 239. ptia register field descriptions field description 7?0 ptia port a input data ? a read always returns the buffered input state of the associated pin.it can be used to detect overload or short circuit conditions on output pins.
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 163 4.28.2.10 port e input register (ptie) 4.28.2.11 pim reserved registers i 4.28.3 functional description 4.28.3.1 registers 4.28.3.1.1 data register (portx) this register holds the value driven out to the pin if the pin is used as a general purpose i/o. writing to this register has only an effect on the pin if the pi n is used as general purpose output. when reading this address, the buffered and synchronized state of the pin is returned if t he associated data direction register bit is set to ?0?. if the data direction register bits are set to logic level ?1?, the contents of the data regist er is returned. this is independ ent of any other configuration ( figure 46 ). 4.28.3.1.2 data direct ion register (ddrx) this register defines whether the pin is used as an input or an output. if a peripher al module controls the pin the contents of the data direction register is ignored ( figure 46 ). 4.28.3.1.3 input register (ptix) this is a read-only register and always returns the buffered and synchronized state of the pin ( figure 46 ). table 240. port e input register (ptie) address 0x0121 access: user read (154) 76543210 r 0 0 0 0 0 0 ptie1 ptie0 w reset (155) uuuuuuuu note: 154. read: anytime. write: unimplemented. writing to this register has no effect. 155. u = unaffected by reset table 241. ptie register field descriptions field description 1?0 ptie port e input data ? a read always returns the buffered input state of the associated pin.it can be used to detect overload or short circuit conditions on output pins. table 242. pim reserved register address 0x0122-0x017f access: user read (156) 76543210 r 0 0 0 0 0 0 0 0 w reset00000000 note: 156. read: anytime. write: unimplemented. writing to this register has no effect.
port integration mo dule (s12ipimv1) mm912_634 advance information, rev. 4.0 freescale semiconductor 164 figure 46. illustration of i/o pin functionality 4.28.3.1.4 reduced driv e register (rdriv) if the pin is used as an output this register allows the configurati on of the drive strength. 4.28.3.1.5 pull device enable register (pucr) this register turns on a pull-up or pull-down device. it becomes active only if the pin is used as an input. 4.28.3.2 ports 4.28.3.2.1 port a this port is associated with the spi. port a pins pa7-0 ca n be used for general-purpose i/o and pa3-0 also with the spi subsystem. 4.28.3.2.2 port c this port is associated with the d2di interf ace. port c pins pc1-0 can be used as the d2di interrupt input and d2di clock outpu t, respectively. a pull-down device is enabled on pin pc1 if used as d2di input.a reduced drive strength can be selected on pc0 if used as d2di output. the d2di interrupt input is synchroni zed and has an asynchronous bypass in stop mode to allow the generation of a wake-up interrupt. 4.28.3.2.3 port d this port is associated with the d2di interface. port d pins pd7-0 can be used with the d2di data i/o. pull-down devices are enabled on all pins if used as d2di inputs.a reduced drive st rength can be selected on all pi ns if used as d2di outputs. 4.28.3.2.4 port e this port is associated with the cpmu osc. port e pins pe1-0 can be used for general-purpose or with the cpmu osc module. 4.28.4 initializat ion information 4.28.4.1 port data and data direction register writes it is not recommended to write ptx and ddrx in a word access. when changing the register pins from inputs to outputs, the data may have extra transitions during the write access. initialize the port data register before enabling the outputs. portx ddrx output enable port enable 1 0 1 0 pin data out periph. data in module 1 0 synch. ptix
mm912_634 advance information, rev. 4.0 freescale semiconductor 165 4.29 memory map co ntrol (s12pmmcv1) 4.29.1 introduction the s12pmmc module controls the access to all internal memories and peripherals for the cpu12 and s12sbdm module. it regulates access priorities and determines t he address mapping of the on-chip resources. figure 47 shows a block diagram of the s12pmmc module. 4.29.1.1 glossary 4.29.1.2 overview the s12pmmc connects the cpu12?s and the s12sbdm?s bus interfaces to the mcu?s on-chip resources (memories and peripherals). it arbitrates the bus accesse s and determines all of the mcu?s memory maps. furthermore, the s12pmmc is responsible for constraining memory accesses on secured devices and for selecting th e mcu?s functional mode. 4.29.1.3 features the main features of this block are: ? paging capability to support a global 256 kbyte memory address space ? bus arbitration between the masters cp u12, s12sbdm to different resources. ? mcu operation mode control ? mcu security control ? separate memory map schemes for each master cpu12, s12sbdm ? generation of system reset when cpu12 accesses an unimp lemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 4.29.1.4 modes of operation the s12pmmc selects the mcu?s functional mode. it also determines the devices behavior in secured and unsecured state. 4.29.1.4.1 functional modes two functional modes are implements on devices of the s12i product family: ? normal single chip (ns) the mode used for running applications. ? special single chip mode (ss) a debug mode which causes the device to enter bdm active mode after each reset. peripherals may also provide special debug features in this mode. table 243. glossary of terms term definition local addresses address within the cpu12?s local address map ( figure 52 ) global address address within the global address map ( figure 52 ) aligned bus access bus acce ss to an even address. misaligned bus access bus access to an odd address. ns normal single-chip mode ss special single-chip mode unimplemented address ranges address ranges wh ich are not mapped to any on-chip resource. p-flash program flash d-plash data flash nvm non-volatile memory; p-flash or d-flash ifr nvm information row. refer to ftmrc block guide
mm912_634 advance information, rev. 4.0 freescale semiconductor 166 4.29.1.4.2 security s12i derives can be secured to prohibit external access to th e on-chip p-flash. the s12pmmc module determines the access permissions to the on-chip memories in secured and unsecured state. 4.29.1.5 block diagram figure 47 shows a block diagram of the s12pmmc. figure 47. s12pmmc block diagram 4.29.2 external signal description the s12pmmc uses two external pins to determi ne the devices operating mode: reset and modc ( table 244 ) see device user guide (dug) for the mapping of these signals to device pins. 4.29.3 memory map and registers 4.29.3.1 module memory map a summary of the register s associated with the s12pmmc block is shown in table 245 . detailed descriptions of the registers and bits are given in the subsections that follow. table 244. external system pins associated with s12pmmc pin name pin functions description reset (see dug) reset the reset pin is used the select the mcu?s operating mode. modc (see dug) modc the modc pin is captured at the rising edge of the reset pin. the captured value determines the mcu?s operating mode. cpu bdm target bus controller dbg mmc address decoder & priority peripherals p-flash d-flash ram
mm912_634 advance information, rev. 4.0 freescale semiconductor 167 4.29.3.2 register descriptions this section consists of th e s12pmmc control register descriptions in address order. 4.29.3.2.1 mode register (mode) read: anytime. write: only if a transition is allowed (see figure 48 ). the modc bit of the mode register is used to select the mcu?s operating mode. table 245. mmc register summary address register name bit 765432 1bit 0 0x000a reserved r000000 0 0 w 0x000b mode r modc 00000 0 0 w 0x0010 reserved r000000 0 0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r000000 0 0 w 0x0013 reserved r000000 0 0 w 0x0013 mmcctl1 r000000 0 ifron w 0x0013 mmcctl1 r00000 ramon romon ifron w 0x0014 reserved r000000 0 0 w 0x0015 ppage r0000 pix3 pix2 pix1 pix0 w = unimplemented or reserved table 246. mode register (mode) address: 0x000b 76543210 r modc 0000000 w reset modc (157) 0000000 = unimplemented or reserved note: 157. external signal (see table 244 ).
mm912_634 advance information, rev. 4.0 freescale semiconductor 168 figure 48. mode transition diagram when mcu is unsecured 4.29.3.2.2 direct page register (direct) read: anytime write: anytime in special ss, write-one in ns. this register determines the position of t he 256 byte direct page within the memory ma p.it is valid for both global and local mapping scheme. figure 49. direct address mapping table 247. mode field descriptions field description 7 modc mode select bit ? this bit controls the current operating m ode during reset high (inactive). the external mode pin modc determines the operating mode during reset low (active). the state of the pin is regi stered into the respective register bit after the reset signal goes inactive (see figure 48 ). write restrictions exist to disall ow transitions between certain modes. figure 48 illustrates all allowed mode changes. attempting non authorized transitions will not change the mode bit, but it will bl ock further writes to the register bit except in special modes. write accesses to the mode register are blocked when the device is secured. table 248. direct register (direct) address: 0x0011 76543210 r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w reset00000000 table 249. direct field descriptions field description 7?0 dp[15:8] direct page index bits 15?8 ? these bits are used by the cpu when performing accesses using the direct addressing mode. these register bits form bits [15:8] of the local address (see figure 49 ). normal single-chip 1 special single-chip 0 (ss) reset (ns) 1 0 1 bit15 bit0 bit7 cpu address [15:0] bit8 dp [15:8]
mm912_634 advance information, rev. 4.0 freescale semiconductor 169 example 1. this example demonstrates usage of the direct addressing mode movb #$80,direct ;set direct register to 0x80. write once only. ;global data accesses to the range 0xxx_80xx can be direct. ;logical data accesses to the range 0x80xx are direct. ldy <$00 ;load the y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are ?direct page aware? and can ;automatically select direct mode. 4.29.3.2.3 mmc contro l register (mmcctl1) read: anytime. write: anytime. the ifron bit of the mmcctl1 register is used to make ifr sector visible in the memory map. the ramon and romon bits of the mmcctl1 register are used to make scra tch-ram and rom visible in the memory map. table 250. mmc control register (mmcctl1) address: 0x0013 76543210 r0000000 ifron w r00000 ramon romon ifron w reset00000000 = unimplemented or reserved table 251. mode field descriptions field description 2 ramon ftmrc scratch-ram visible in the memory map write: anytime this bit is used to make the ftmrc scratc h-ram visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map and accessible via ppage 0x01 1 romon ftmrc rom visible in the memory map write: anytime this bit is used to make the ftmrc rom visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map and accessible via ppage 0x01 0 ifron ifr visible in the memory map write: anytime this bit is used to make the ifr sect or visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map and accessible via ppage 0x01
mm912_634 advance information, rev. 4.0 freescale semiconductor 170 4.29.3.2.4 program page index register (ppage) read: anytime write: anytime these four index bits are used to map 16 kb blocks into the flash page window located in the local (cpu or bdm) memory map from address 0x8000 to address 0xbfff (see figure 50 ). this supports accessing up to 256 kb of flash (in the global map) within the 6 kb local map. the ppage index register is effectiv ely used to construct paged flash addresses in the local map format. the cpu has special access to read and write this regist er directly during execution of call and rtc instructions. figure 50. page address mapping note writes to this register using the special a ccess of the call and rtc instructions will be complete before the end of the instruction execution. the fixed 16 kb page from 0x0000 to 0x3fff is the page number 0x 0c. parts of this page are covered by registers, d-flash and ram space. see soc guide for details. the fixed 16 kb page from 0x4000?0x7fff is the page number 0x0d. the reset value of 0x0e ensures that there is linear flash space available between addresses 0x0000 and 0xffff out of reset. the fixed 16 kb page from 0xc000-0xffff is the page number 0x0f. 4.29.4 functional description the s12pmmc block performs several basic functions of the s12i sub-system operation: mcu operatio n modes, priority control, address mapping, select signal generation and access limitations for the system . each aspect is de scribed in the following subsections. table 252. program page index register (ppage) address: 0x0030 76543210 r0 0 0 0 pix3 pix2 pix1 pix0 w reset00001110 table 253. ppage field descriptions field description 3?0 pix[3:0] program page index bits 3?0 ? these page index bits are used to select which of the 256 p-flash or rom array pages is to be accessed in the program page window. bit14 bit0 address [13:0] ppage register [3:0] global address [17:0] bit13 bit17 address: cpu local address or bdm local address
mm912_634 advance information, rev. 4.0 freescale semiconductor 171 4.29.4.1 mcu operating modes ? normal single chip mode this is the operation mode for running applicati on code. there is no external bus in this mode. ? special single chip mode this mode is generally used for debugging operation, boot- strapping or security related operations. the active background debug mode is in control of the cpu code execut ion and the bdm firmware is waiting for serial commands sent through the bkgd pin. 4.29.4.2 memory map scheme 4.29.4.2.1 cpu and bdm memory map scheme the bdm firmware lookup tables and bdm register memory loca tions share addresses with other modules; however they are not visible in the memory map during user?s code execution. the bdm memory resources are enabled only during the read_bd and write_bd access cycles to distinguish between accesses to the bdm memory area and accesses to the other modules. (refer to bdm block guide for further details). when the mcu enters active bdm mode, th e bdm firmware lookup tables and the bdm registers become visible in the local memory map in the range 0xff00-0xffff (global address 0x3_ff00 - 0x3_ffff) and the cpu begins execution of firmware commands or the bdm begins execution of hardware comman ds. the resources which share memory space with the bdm module will not be visible in the memory map during active bdm mode. please note that after the mcu enters active bdm mode the bd m firmware lookup tables and the bdm registers will also be visible between addresses 0xbf00 and 0xbfff if the ppage register contains value of 0x0f. 4.29.4.2.1.1 expansion of the local address map expansion of the cpu local address map the program page index register in s12pmmc allows accessing up to 256 kb of p-flash in the global memory map by using the four index bits (ppage[3:0]) to page 16x16 kb blocks into th e program page window located from address 0x8000 to address 0xbfff in the local cpu memory map. the page value for the program page window is stored in the ppag e register. the value of the pp age register can be read or written by normal memory accesses as well as by the call and rtc instructions (see section 4.29.6.1, ?call and rtc instructions ). control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64 kb local cpu address space. the starting address of an interrupt servic e routine must be located in unpaged memory unless the user is certain that the ppag e register will be set to the appropriate va lue when the service routine is called. howe ver an interrupt service routine can call other routines that are in paged memory. the upper 16 kb block of t he local cpu memory space (0xc000?0xffff) is unpaged. it is recommended that all reset and interrupt vectors point to location s in this area or to the other unmapped pages sections of the local cpu memory map. expansion of the bdm local address map ppage and bdmppr register is also used for the expansion of the bdm local address to the global address. these registers can be read and written by the bdm. the bdm expansion scheme is the sa me as the cpu expansion scheme. the four bdmppr program page index bits allow access to t he full 256 kb address map that can be accessed with 18 address bits. the bdm program page index register (bdmppr) is used only when t he feature is enabled in bdm and, in the case the cpu is executing a firmware command which uses cpu instructions, or by a bdm hardware commands. see the bdm block guide for further details. (see figure 51 ).
mm912_634 advance information, rev. 4.0 freescale semiconductor 172 figure 51. bdmppr address mapping bdm hardware command bdm firmware command bit14 bit0 bdm local address [13:0] bdmppr register [3:0] global address [17:0] bit13 bit17 bit14 bit0 cpu local address [13:0] bdmppr register [3:0] global address [17:0] bit13 bit17
mm912_634 advance information, rev. 4.0 freescale semiconductor 173 figure 52. local to global address mapping 0x3_ffff ppage cpu and bdm local memory map global memory map 0xffff 0xc000 0x8000 p-flash window 0x3_4000 0x3_8000 0x3_c000 0x0_4000 0x0000 0x4000 0x0400 d-flash ram unpaged p-flash registers unpaged p-flash unpaged p-flash 0 p0 p1 p2 p3 0 0 0 0x1400 ramsize 0x0_0000 ram ramsize 10 *16k paged p-flash 0x0_8000 nvm resources registers ram_low unpaged p-flash 0x3_0000 unimplemented area unpaged p-flash unpaged p-flash (ppage 0x0c) (ppage 0x0d) (ppage 0x0e) (ppage 0x0f) unpaged p-flash or (ppage 0x02-0x0b)) (ppage 0x01) (ppage 0x00) unpaged p-flash 0x0_4400 d-flash 0x0_5400 nvm resources
mm912_634 advance information, rev. 4.0 freescale semiconductor 174 4.29.5 implemented memory in the system memory architecture each memory can be implemented in its maximum allowed size. but some devices have been defined for smaller sizes, which means less implemented pages. all non implem ented pages are called unimplemented areas. ? registers has a fixed size of 1.0 kb, accessible via xbus0. ? sram has a maximum size of 11 kb, accessible via xbus0. ? d-flash has a fixed size of 4.0 kb accessible via xbus0. ? p-flash has a maximum size of 224 kb, accessible via xbus0. ? nvm resources (ifr, scratch-ram, rom) including d- flash have maximum size of 16 kb (ppage 0x01). these resources are visible on the memory map by enab ling the appropriate bits on mmcctl1 register (see figure 250 ) 4.29.5.0.1 implemented memory map the global memory spaces reserved for the internal resource s (ram, d-flash, and p-flash) are not determined by the mmc module. size of the individual internal resources are however fi xed in the design of the device cannot be changed by the user. please refer to the soc guide for further details. figure 53 and table 254 show the memory spaces occupied by the on-chip resources. please note that the memory spaces have fixed top addresses. in single-chip modes accesses by the cpu12 (except for fi rmware commands) to any of the unimplemented areas (see figure 53 ) will result in an illegal access reset (system reset). bdm accesses to the uni mplemented areas are allowed but the data will be undefined. no misaligned word access from the bdm module will occur; these accesses are blocked in the bdm module (refer to bdm block guide). table 254. global implemented memory space internal resource bottom address top address registers 0x0_0000 0x0_03ff system ram ram_low = 0x0_4000 minus ramsize (158) 0x0_3fff ftmrc ifr (if mmcctl1.ifron == 1?b1) 0x0_4000 0x0_43ff d-flash 0x0_4400 0x0_53ff ftmrc scratch-ram (if mmcctl1.ramon == 1?b1) 0x0_5800 0x0_5800 plus scr-ramsize ftmrc rom (if mmcctl1.romon == 1?b1) 0x0_8000 minus romsize 0x0_7fff p-flash pf_low = 0x4_0000 minus flashsize (159) 0x3_ffff note: 158. ramsize is the hexadecimal value of ram size in bytes 159. flashsize is the hexadecimal value of flash size in bytes
mm912_634 advance information, rev. 4.0 freescale semiconductor 175 figure 53. implemented global address mapping 4.29.5.1 chip bus control the s12pmmc controls the address buses and the data buses that interface the bus masters (cpu12, s12sbdm) with the rest of the system (master buses). in addition the mmc handles all cpu read data bus swapping operations. all internal resources are connected to specific target buses (see figure 54 ). 0x3_ffff ppage cpu and bdm local memory map global memory map 0xffff 0xc000 0x8000 p-flash window pf_low unpaged p-flash unpaged p-flash 0 p0 p1 p2 p3 0 0 0 pfsize unimplemented area p-flash 0x0000 0x4000 0x0400 d-flash ram unpaged p-flash registers 0x1400 ramsize 0x0_4000 0x0_0000 ram ramsize 0x0_8000 nvm resources registers ram_low unimplemented area (ppage 0x01) (ppage 0x00) 0x0_4400 d-flash 0x0_5400 nvm resources
mm912_634 advance information, rev. 4.0 freescale semiconductor 176 figure 54. s12i platform 4.29.5.1.1 master bus priori tization regarding access conflicts on target buses the arbitration scheme allows only one mast er to be connected to a target at any given time. the following rules apply when prioritizing accesses from different masters to the same target bus: ? cpu12 always has priority over bdm. ? bdm has priority over cpu12 when its access is stalled for more than 128 cycles. in the later case the cpu will be stalled after finishing the current operation and the bdm will gain access to the bus. 4.29.5.2 interrupts the mmc does not generate any interrupts. 4.29.6 initialization/a pplication information 4.29.6.1 call and rtc instructions call and rtc instructions are uninterruptable cpu instructions that automate page switching in the program page window. the call instruction is similar to the jsr inst ruction, but the subroutine that is calle d can be located anywhere in the local addr ess space or in any flash or rom page visible through the prog ram page window. the call instruction calculates and stacks a return address, stacks the current ppage value and writes a ne w instruction-supplied value to the ppage register. the ppage value controls which of the 256 possible pages is visible th rough the 16 kbyte program page window in the 64 kbyte local cpu memory map. execution then begins at the address of the called subroutine. during the execution of the call instruct ion, the cpu performs the following steps: 1. writes the current ppage value into an internal tempor ary register and writes the new instruction-supplied ppage value into the ppage register 2. calculates the address of the next instruction after the call instruction (the return address) and pushes this 16-bit value onto the stack 3. pushes the temporarily stor ed ppage value onto the stack 4. calculates the effective address of the subroutine, refills the queue and begins ex ecution at the new address this sequence is uninterruptable. there is no need to inhibit in terrupts during the call instruction execution. a call instruct ion can be performed from any address to any other address in the local cpu memory space. the ppage value supplied by the instruction is part of the effe ctive address of the cpu. for all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the inst ruction. in indexed-indirect variations of the call instruction a pointe r specifies memory locations where the new page value and the address of the called subroutine are stored. using indirect addressing for both the ne w page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the time of assembly. cpu bdm mmc ?crossbar switch? s12x0 xbus0 dbg s12x1 ipbi p-flash d-flash sram bdm resources peripherals
mm912_634 advance information, rev. 4.0 freescale semiconductor 177 4.30 interrupt module (s12sintv1) 4.30.1 introduction the int module decodes the priori ty of all system exception requ ests and provides the applicab le vector for processing the exception to the cpu. the int module supports: ? i bit and x bit maskable interrupt requests ? a non-maskable unimplemented op-code trap ? a non-maskable software interrupt (swi) or background debug mode request ? three system reset vector requests ? a spurious interrupt vector each of the i bit maskable interrupt reques ts is assigned to a fixed priority level. 4.30.1.1 glossary table 255 contains terms and abbreviations used in the document. 4.30.1.2 features ? interrupt vector base register (ivbr) ? one spurious interrupt vector (at address vector base (160) + 0x0080). ? 2?58 i bit maskable interrupt vector requests (at addresses vector base + 0x0082?0x00f2). ? i bit maskable interrupts can be nested. ? one x bit maskable interrupt vector request (at address vector base + 0x00f4). ? one non-maskable software interrupt request (swi) or ba ckground debug mode vector request (at address vector base + 0x00f6). ? one non-maskable unimplemented op-code trap (tr ap) vector (at address vector base + 0x00f8). ? three system reset vectors (a t addresses 0xfffa?0xfffe). ? determines the highest priority interrupt vector reques ts, drives the vector to the bus on cpu request ? wakes up the system from stop mode when an appropriate interrupt request occurs. note: 160. the vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (ivbr, use d as upper byte) and 0x00 (used as lower byte). 4.30.1.3 modes of operation ?run mode this is the basic mode of operation. ? stop mode in stop mode, the clock to the int module is disabled. the int module is however capable of waking-up the cpu from stop mode if an interrupt occurs. please refer to section 4.30.5.3, ?wake-up from stop mode? for details. ? freeze mode (bdm active) in freeze mode (bdm active), the interrupt vector bas e register is overridden internally. please refer to section 4.30.3.1.1, ?interrupt vector base register (ivbr)? for details. 4.30.1.4 block diagram figure 55 shows a block diagram of the int module. table 255. terminology term meaning ccr condition code register (in the cpu) isr interrupt service routine mcu micro-controller unit
mm912_634 advance information, rev. 4.0 freescale semiconductor 178 figure 55. int block diagram 4.30.2 external signal description the int module has no external signals. 4.30.3 memory map and register definition this section provides a detailed description of all registers accessible in the int module. 4.30.3.1 register descriptions this section describes in address order all the int registers and their individual bits. 4.30.3.1.1 interrupt vector base register (ivbr) read: anytime write: anytime table 256. interrupt vector base register (ivbr) address: 0x001f 76543210 r ivb_addr[7:0] w reset11111111 table 257. ivbr field descriptions field description 7?0 ivb_addr[7:0] interrupt vector base address bits ? these bits represent the upper byte of all vector addresses. out of reset these bits are set to 0xff (i.e., vectors are located at 0xff80?0xfffe) to ensure compatibility to hcs12. note: a system reset will initialize the interrupt vector base register with ?0xff? before it is used to determine the reset vector address. therefore, changing the ivbr has no effect on the location of the three reset vectors (0xfffa?0xfffe). note: if the bdm is active (i.e., the cpu is in the process of executing bdm firmware code), the contents of ivbr are ignored and the upper byte of the vector address is fixed as ?0xff?. this is done to enable handling of all non-maskable interrupts in the bdm firmware. wake-up ivbr interrupt requests interrupt requests cpu vector address peripheral to c p u priority decoder non i bit maskable channels i bit maskable channels
mm912_634 advance information, rev. 4.0 freescale semiconductor 179 4.30.4 functional description the int module processes all exception requests to be serviced by the cpu module. these exceptions include interrupt vector requests and reset vector requests. each of these exception types and their overall pr iority level is discussed in the subsecti ons below. 4.30.4.1 s12s exception requests the cpu handles both reset requests and interrupt requests. a pr iority decoder is used to ev aluate the priority of pending interrupt requests. 4.30.4.2 interrupt prioritization the int module contains a priority decoder to determine the priority for all interrupt requests pending for the cpu. if more th an one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization. the following conditions must be met for an i b it maskable interrupt request to be processed. 1. the local interrupt enabled bit in the peripheral module must be set. 2. the i bit in the condition code regist er (ccr) of the cpu must be cleared. 3. there is no swi, trap, or x bit maskable request pending. note all non i bit maskable interrupt requests alwa ys have higher priority than the i bit maskable interrupt requests. if the x bit in the ccr is cleared, it is possible to interrupt an i bit maskable interrupt by an x bit maskable interrupt. it is possible to nest non maskable interrupt requests, e.g., by nesting swi or trap calls. since an interrupt vector is only supplied at the time when the cpu requests it, it is possible that a higher priority interrup t request could override the original interrupt reque st that caused the cpu to request the vect or. in this case, the cpu will receive the highest priority vector and the system will process this interru pt request first, before the or iginal interrupt request is proc essed. if the interrupt source is unknown (for ex ample, in the case where an interrupt re quest becomes inactive after the interrupt ha s been recognized, but prior to the cpu vector request), the vector address supplied to t he cpu will default to that of the spuri ous interrupt vector. note care must be taken to ensure that all inte rrupt requests remain active until the system begins execution of the applicable service routin e; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt reque st (vector at address (vector base + 0x0080)). 4.30.4.3 reset exception requests the int module supports three system reset exception request type s (please refer to the clock and reset generator module for details): 1. pin reset, power-on reset or illegal addre ss reset, low voltage reset (if applicable) 2. clock monitor reset request 3. cop watchdog reset request 4.30.4.4 exception priority the priority (from highest to lowest) and address of all excepti on vectors issued by the int modu le upon request by the cpu is shown in ta b l e 2 5 8 . table 258. exception vector map and priority vector address (161) source 0xfffe pin reset, power-on reset, illegal addr ess reset, low voltage reset (if applicable) 0xfffc clock monitor reset 0xfffa cop watchdog reset (vector base + 0x00f8) unimplemented opcode trap (vector base + 0x00f6) software interrupt instruction (swi) or bdm vector request
mm912_634 advance information, rev. 4.0 freescale semiconductor 180 4.30.5 initialization/a pplication information 4.30.5.1 init ialization after system reset, software should: 1. initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xff80?0xfff9). 2. enable i bit maskable interrupts by clearing the i bit in the ccr. 3. enable the x bit maskable interrupt by clearing the x bit in the ccr. 4.30.5.2 interru pt nesting the interrupt request scheme makes it possible to nest i bit maskable interrupt requests handled by the cpu. i bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority. i bit maskable interrupt requests cannot be interrupted by other i b it maskable interrupt requests per default. in order to make an interrupt service routine (isr) interruptible, the isr must expl icitly clear the i bit in the ccr (cli). after clearing the i bit , other i bit maskable interrupt requests can interrupt the current isr. an isr of an interruptible i bit maskable interrupt request could basically look like this: 1. service interrupt, e.g., clear interrupt flags, copy data, etc. 2. clear i bit in the ccr by executing the instruction cli (thus allowing othe r i bit maskable interrupt requests) 3. process data 4. return from interrupt by executing the instruction rti 4.30.5.3 wake-up from stop mode 4.30.5.3.1 cpu wake-up from stop mode every i bit maskable interrupt request is capable of waking the mcu from stop mode. to determ ine whether an i bit maskable interrupts is qualified to wake-up the cpu or not, the same condi tions as in normal run mode are applied during stop mode: if t he i bit in the ccr is set, all i bit maskable interrupts are masked from waking-up the mcu. since there are no clocks running in stop mode, only interrupts which can be asse rted asynchronously can wake-up the mcu from stop mode. the x bit maskable interrupt request can wake up the mcu fr om stop mode at anytime, even if the x bit in ccr is set. if the x bit maskable interrupt request is used to wake-up the m cu with the x bit in the ccr set, the associated isr is not cal led. the cpu then resumes program execution wit h the instruction following the wai or stop instruction. this features works the same rules like any interrupt request, i.e. care must be taken that the x interrupt request used for wake-up remains active at least until the system begins ex ecution of the instruction followi ng the wai or stop instruction; otherwise, wake-up may not occur. (vector base + 0x00f4) x bit maskable interr upt request (xirq or d2d error interrupt) (162) (vector base + 0x00f2) irq or d2d interrupt request (163) (vector base + 0x00f0?0x0082) device specific i bit maskable interru pt sources (priority determined by the low byte of the vector address, in descending order) (vector base + 0x0080) spurious interrupt note: 161. 16 bits vector address based 162. d2d error interrupt on mcus featuring a d2d initiator module, otherwise xirq pin interrupt 163. d2d interrupt on mcus featuring a d2d initiator module, otherwise irq pin interrupt table 258. exception vector map and priority vector address (161) source
mm912_634 advance information, rev. 4.0 freescale semiconductor 181 4.31 background debug module (s12sbdmv1) 4.31.1 introduction this section describes the functionalit y of the background debug module (bdm) sub-block of the hcs12s core platform. the background debug module (bdm) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal cpu intervention. all interfac ing with the bdm is done via the bkgd pin. the bdm has enhanced capability for maintaining synchronization be tween the target and host while allowing more flexibility in clock rates. this includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. th e system is backwards compatible to the bdm of the s12 family with t he following exceptions: ? taggo command not su pported by s12sbdm ? external instruction tagging feat ure is part of the dbg module ? s12sbdm register map and register content modified ? family id readable from bdm rom at global address 0x3_ff 0f in active bdm (value for devices with hcs12s core is 0xc2) ? clock switch removed from bdm (clksw bit removed from bdmsts register) 4.31.1.1 features the bdm includes these distinctive features: ? single-wire communication with host development system ? enhanced capability for allowing more flexibility in clock rates ? sync command to determine communication rate ? go_until(171) command ? hardware handshake protocol to increase the performance of the serial communication ? active out of reset in special single chip mode ? nine hardware commands using free cycles, if available, for minimal cpu intervention ? hardware commands not requiring active bdm ? 14 firmware commands execute from the standard bdm firmware lookup table ? when secured, hardware commands are allowed to access the r egister space in special single chip mode, if the flash erase tests fail. ? family id readable from bdm rom at global address 0x3_ff 0f in active bdm (value for devices with hcs12s core is 0xc2) ? bdm hardware commands are operational until system stop mode is entered 4.31.1.2 modes of operation bdm is available in all operating modes but must be enabled be fore firmware commands are exec uted. some systems may have a control bit that allows suspending the function during background debug mode. 4.31.1.2.1 regular run modes all of these operations refer to the part in run mode and not be ing secured. the bdm does not pr ovide controls to conserve powe r during run mode. ? normal modes general operation of the bdm is available and operates the same in all normal modes. ? special single chip mode in special single chip mode, background operation is enabled and active out of reset.this allows programming a system with blank memory. 4.31.1.2.2 secure mode operation if the device is in secure mode, the operati on of the bdm is reduced to a small subset of its regular run mode operation. secur e operation prevents access to flash other than a llowing erasure. for more information please see section 4.31.4.1, ?security? . 4.31.1.2.3 low-power modes the bdm can be used until stop mode is entered. the cpu cannot enter stop mode during bdm active mode.
mm912_634 advance information, rev. 4.0 freescale semiconductor 182 in stop mode the bdm clocks ar e stopped. when bdm clocks are disabled and stop mode is exit ed, the bdm clocks will restart and bdm will have a soft reset (clearing the instruction regist er, any command in progress and disable the ack function). the bdm is now ready to receive a new command. 4.31.1.3 block diagram a block diagram of the bdm is shown in figure 56 . figure 56. bdm block diagram 4.31.2 external signal description a single-wire interface pin called the background debug interf ace (bkgd) pin is used to communicate with the bdm system. during reset, this pin is a mode select input which selects betwe en normal and special modes of operation. after reset, this pi n becomes the dedicated serial interface pin for the background debug mode. 4.31.3 memory map and register definition 4.31.3.1 module memory map table 259 shows the bdm memory map when bdm is active. table 259. bdm memory map global address module size (bytes) 0x3_ff00?0x3_ff0b bdm registers 12 0x3_ff0c?0x3_ff0e bdm firmware rom 3 0x3_ff0f family id (part of bdm firmware rom) 1 0x3_ff10?0x3_ffff bdm firmware rom 240 16-bit shift register bkgd host system serial interface data control register block register bdmsts instruction code and execution standard bdm firmware lookup table secured bdm firmware lookup table bus interface and control logic address data control clocks bdmact trace enbdm sdv unsec
mm912_634 advance information, rev. 4.0 freescale semiconductor 183 4.31.3.2 register descriptions a summary of the registers associated with the bdm is shown in table 260 . registers are accessed by host-driven communications to the bdm hardware using read_bd and write_bd commands. table 260. bdm register summary global address register name bit 7654321bit 0 0x3_ff00 reserved rxxxxxx0 0 w 0x3_ff01 bdmsts r enbdm bdmact 0 sdv trace 0 unsec 0 w 0x3_ff02 reserved rxxxxxxxx w 0x3_ff03 reserved rxxxxxxxx w 0x3_ff04 reserved rxxxxxxxx w 0x3_ff05 reserved rxxxxxxxx w 0x3_ff06 bdmccr r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w 0x3_ff07 reserved r00000000 w 0x3_ff08 bdmppr r bpae 000 bpp3 bpp2 bpp1 bpp0 w 0x3_ff09 reserved r00000000 w 0x3_ff0a reserved r00000000 w 0x3_ff0b reserved r00000000 w = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero
mm912_634 advance information, rev. 4.0 freescale semiconductor 184 4.31.3.2.1 bdm status register (bdmsts) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured, but subject to the following: ? enbdm should only be set via a bdm hardware command if the bdm firmware commands are needed. (this does not apply in special single chip mode). ? bdmact can only be set by bdm hardware upon entry into bdm. it can only be cleared by the standard bdm firmware lookup table upon exit from bdm active mode. ? all other bits, while writable via bdm hardware or stand ard bdm firmware write command s, should only be altered by the bdm hardware or standard firmware lo okup table as part of bdm command execution. register global address 0x3_ff01 table 261. bdm status register ( bdmsts) 76543210 r enbdm bdmact 0 sdv trace 0 unsec 0 w reset special single-chip mode 0 (164) 100000 (165) 0 all other modes 0 0000000 = unimplemented, reserved = implemented (do not alter) 0 = always read zero note: 164. enbdm is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but ful ly erased (flash). this is because the enbdm bit is set by the standar d bdm firmware before a bdm command can be fully transmitted and executed. 165. unsec is read as 1 by a debugging environment in special sing le chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). table 262. bdmsts field descriptions field description 7 enbdm enable bdm ? this bit controls whether the bdm is enabled or di sabled. when enabled, bdm can be made active to allow firmware commands to be executed. when disabled, bdm cannot be made active but bdm hardware commands are still allowed. 0 bdm disabled 1 bdm enabled note: enbdm is set out of reset in special single chip mode. in special single chip mode with the device secured, this bit will not be set until after the flash erase verify tests are complete. 6 bdmact bdm active status ? this bit becomes set upon entering bdm. the standard bdm firmware lookup table is then enabled and put into the memory map. bdmact is cleared by a carefully timed store instruction in the standard bdm firmware as part of the exit sequence to return to user code and remove the bdm memory from the map. 0 bdm not active 1 bdm active 4 sdv shift data valid ? this bit is set and cleared by the bdm hardware. it is set after data has been transmitted as part of a bdm firmware or hardware read command or after data has been received as part of a bdm firmware or hardware write command. it is cleared when the next bdm command has been received or bd m is exited. sdv is used by the standard bdm firmware to control program flow execution. 0 data phase of command not complete 1 data phase of command is complete
mm912_634 advance information, rev. 4.0 freescale semiconductor 185 read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured note when bdm is made active, the cpu stores the content of its ccr register in the bdmccr register. however, out of special single-chip reset, the bdmccr is set to 0xd8 and not 0xd0 which is the reset value of the ccr register in this cpu mode. out of reset in all other modes the bdmccr register is read zero. when entering background debug mode, the bdm ccr holding register is used to save the condition code register of the user?s program. it is also used for temporary st orage in the standard bdm firmware mode. the bdm ccr holding register can be written to modify the ccr value. 4.31.3.2.2 bdm program page index register (bdmppr) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured 3 trace trace1 bdm firmware command is being executed ? this bit gets set when a bdm trace1 firmware command is first recognized. it will stay set until bd m firmware is exited by one of the following bdm commands: go or go_until(171). 0 trace1 command is not being executed 1 trace1 command is being executed 1 unsec unsecure ? if the device is secured this bit is only writable in special single chip m ode from the bdm secure firmware. it is in a zero state as secure mode is entered so that the secu re bdm firmware lookup table is enabled and put into the memory map overlapping the standard bdm firmware lookup table. the secure bdm firmware lookup table verifies that the on-chip flash is erased. this being the case, the unsec bit is set and the bdm program jumps to the start of the standard bdm firmware lookup table and the secure bdm firmware lookup table is turned off. if the erase test fails, the unsec bit will not be asserted. 0 system is in a secured mode. 1 system is in a unsecured mode. note: when unsec is set, security is off and the user can chang e the state of the secure bits in the on-chip flash eeprom. note that if the user does not change the state of the bits to ?unsecured? mode, the system will be secured again when it is next taken out of reset.after reset this bit has no meaning or effect when the security byte in the flash eeprom is configured for unsecure mode. register global address 0x3_ff06 table 263. bdm ccr holding register (bdmccr) 76543210 r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w reset special single-chip mode11011000 all other modes 0 0000000 register global address 0x3_ff08 table 264. bdm program page register (bdmppr) 76543210 r bpae 000 bpp3 bpp2 bpp1 bpp0 w reset00000000 = unimplemented, reserved table 262. bdmsts field descriptions (continued) field description
mm912_634 advance information, rev. 4.0 freescale semiconductor 186 4.31.3.3 family id assignment the family id is an 8-bit value located in the bdm rom in acti ve bdm (at global address: 0x3_ff0f). the read-only value is a unique family id which is 0xc2 for devices with an hcs12s core. 4.31.4 functional description the bdm receives and executes commands from a host via a single wire serial interface. there are two types of bdm commands: hardware and firmware commands. hardware commands are used to read and write target system me mory locations and to enter active background debug mode, see section 4.31.4.3, ?bdm hardware commands? . target system memory includes all me mory that is accessible by the cpu. firmware commands are used to read and write cpu resour ces and to exit from active background debug mode, see section 4.31.4.4, ?standard bdm firmware commands? . the cpu resources referred to ar e the accumulator (d), x index register (x), y index register (y), sta ck pointer (sp), and program counter (pc). hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see section 4.31.4.3, ?bdm hardware commands? ) and in secure mode (see section 4.31.4.1, ?security? ). bdm firmware commands can only be executed when th e system is not secure and is in active background debug mode (bdm). 4.31.4.1 security if the user resets in to special single chip mode with t he system secured, a secured mode bdm firmware lookup table is brought into the map overlapping a portion of the standard bdm firmware lo okup table. the secure bdm firm ware verifies that the on-chip flash eeprom are erased. this being the case, the unsec and enbdm bit will get set. the bdm program jumps to the start of the standard bdm firmware and the secured mode bdm firmware is turned off and all bdm commands are allowed. if the flash do not verify as erased, the bdm firmware sets the enbdm bit, without asserting unsec, and the firmware enters a loop. this causes the bdm hardware commands to become enabled, but does not enable the firmware commands. this allows the bdm hardware to be used to erase the flash. bdm operation is not possible in any other mode than special si ngle chip mode when the device is secured. the device can only be unsecured via bdm serial interface in special single chip mode. for more information rega rding security, please see the s12s_9sec block guide. 4.31.4.2 enabling and activating bdm the system must be in active bdm to execute standard bd m firmware commands. bdm can be activated only after being enabled. bdm is enabled by setting the enbdm bit in the bdm stat us (bdmsts) register. the enbdm bit is set by writing to the bdm status (bdmsts) register, via the single-wire interf ace, using a hardware command such as write_bd_byte. after being enabled, bdm is activated by one of the following (166) : ? hardware background command ? cpu bgnd instruction ? breakpoint force or tag mechanism (167) when bdm is activated, the cpu finishes executing the current instruction and then begins executing the firmware in the standard bdm firmware lookup table. when bdm is activated by a breakpoint, the type of breakpoint used determines if bdm becomes active before or after execution of the next instruction. note: 166. bdm is enabled and active immediatel y out of special single-chip reset. 167. this method is provided by the s12s_dbg module. table 265. bdmppr field descriptions field description 7 bpae bdm program page access enable bit ? bpae enables program page access for bdm hardware and firmware read/write instructions. the bdm hardware commands used to access the bdm registers (read_bd and write_bd) can not be used for global accesses even if the bgae bit is set. 0 bdm program paging disabled 1 bdm program paging enabled 3?0 bpp[3:0] bdm program page index bits 3?0 ? these bits define the selected program page. for more detailed information regarding the program page window scheme, please refer to the s12s_mmc block guide.
mm912_634 advance information, rev. 4.0 freescale semiconductor 187 note if an attempt is made to activate bdm before being enabled, the cpu resumes normal instruction execution after a brief dela y. if bdm is not enabled, any hardware background commands issued are ignored by the bdm and the cpu is not delayed. in active bdm, the bdm registers and standard bdm firmwar e lookup table are mapped to addresses 0x3_ff00 to 0x3_ffff. bdm registers are mapped to addresses 0x3_ff00 to 0x3_ff0b. the bdm uses these registers which are readable anytime by the bdm. however, these registers are not readable by user programs. when bdm is activated while cpu executes code overlapping wit h bdm firmware space the saved program counter (pc) will be auto incremented by one from the bdm firmware, no matter what caused the entry into bdm acti ve mode (bgnd instruction, background command or breakpoints). in such a case the pc must be set to the next valid address via a write_pc command before executing the go command. 4.31.4.3 bdm hardware commands hardware commands are used to read and write target system me mory locations and to enter active background debug mode. target system memory includes all memory t hat is accessible by the cpu such as on-ch ip ram, flash, i/o and control registers. hardware commands are executed with mi nimal or no cpu intervention and do not re quire the system to be in active bdm for execution, although, they can st ill be executed in this mode. when executing a hardware command, the bdm sub-block waits for a free bus cycle so that the background access does not distur b the running application program. if a free cycle is not found w ithin 128 clock cycles, the cpu is momentarily fr ozen so that the bdm can steal a cycle. when the bdm finds a free cycle, the operation does not intrude on normal cpu operation provided that it ca n be completed in a single cycle. however, if an operatio n requires multiple cycles the cpu is frozen until th e operation is complete, even t hough the bdm foun d a free cycle. the bdm hardware commands are listed in table 266 . the read_bd and write_bd commands allow access to the bdm register locations. these locations are not normally in the system memory map but share addresses with the application in me mory. to distinguish between physical memory locations that share the same address, bdm memory resources are enabled ju st for the read_bd and write_bd access cycle. this allows the bdm to access bdm locations unobtrusively, even if the addresses conflict with the application memory map. table 266. hardware commands command opcode (hex) data description background 90 none enter background mode if bdm is enabled. if enabled, an ack will be issued when the part enters active background mode. ack_enable d5 none enable handshake. issues an ack pulse after the command is executed. ack_disable d6 none disable handshake. this command does not issue an ack pulse. read_bd_byte e4 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table in map. odd address data on low byte; even address data on high byte. read_bd_word ec 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table in map. must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table out of map. odd address data on low byte; even address data on high byte. read_word e8 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table out of map. must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table in map. odd address data on low byte; even address data on high byte. write_bd_word cc 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table in map. must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table out of map. odd address data on low byte; even address data on high byte. write_word c8 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table out of map. must be aligned access. note: 168. if enabled, ack will occur when data is ready for transmission for all bdm read co mmands and will occur after the write is complete for all bdm write commands.
mm912_634 advance information, rev. 4.0 freescale semiconductor 188 4.31.4.4 standard bdm firmware commands bdm firmware commands are used to access and manipulate cpu resources. the system must be in active bdm to execute standard bdm firmware commands, see section 4.31.4.2, ?enabling and activating bdm? . normal instruction execution is suspended while the cpu executes the firmware located in the standard bdm firmware lookup table. the hardware command background is the usual way to activate bdm. as the system enters active bdm, the st andard bdm firmware lookup table and bd m registers become visible in the on-chip memory map at 0x3_ff00?0x3_ffff, and the cpu begins executing the standard bdm firmware. the standard bdm firmware watches for serial commands and executes them as they are received. the firmware commands are shown in ta b l e 2 6 7 . 4.31.4.5 bdm command structure hardware and firmware bdm commands start with an 8-bit opc ode followed by a 16-bit address and/or a 16-bit data word, depending on the command. all the read commands return 16 bits of data despite the byte or word implication in the command name.{satatement} 8-bit reads return 16-bits of data, only one by te of which contains valid data. if reading an even address, the valid data will appear in the m sb. if reading an odd address, the valid data will appear in the lsb. table 267. firmware commands command (169) opcode (hex) data description read_next (170) 62 16-bit data out increment x index register by 2 (x = x + 2), then read word x points to. read_pc 63 16-bit data out read program counter. read_d 64 16-bit data out read d accumulator. read_x 65 16-bit data out read x index register. read_y 66 16-bit data out read y index register. read_sp 67 16-bit data out read stack pointer. write_next 42 16-bit data in increment x index register by 2 (x = x + 2), then write word to location pointed to by x. write_pc 43 16-bit data in write program counter. write_d 44 16-bit data in write d accumulator. write_x 45 16-bit data in write x index register. write_y 46 16-bit data in write y index register. write_sp 47 16-bit data in write stack pointer. go 08 none go to user program. if enabled, ack will occur when leaving ac tive background mode. go_until (171) 0c none go to user program. if enabled, ack wi ll occur upon returning to active background mode. trace1 10 none execute one user instruction then return to active bdm. if enabled, ack will occur upon returning to active background mode. taggo -> go 18 none (previous enable tagging and go to user program.) this command will be deprecated and should not be used anymore. opcode will be executed as a go command. note: 169. if enabled, ack will occur when data is ready for transmission for all bdm read co mmands and will occur after the write is complete for all bdm write commands. 170. when the firmware command read_next or write_next is us ed to access the bdm address space the bdm resources are accessed rather than user code. writing bdm firmware is not possible. 171. system stop disables the ack function and ignored commands wi ll not have an ack-pulse (e.g., cpu in stop mode). the go_unti l command will not get an acknowledge if cpu executes the stop in struction before the ?until? condi tion (bdm active again) is rea ched (see section 4.31.4.7, ?serial interface hardware handshake protocol? last note).
mm912_634 advance information, rev. 4.0 freescale semiconductor 189 16-bit misaligned reads and writes are generally not allowed. if attempted by bdm hardware command, the bdm ignores the least significant bit of the address and assumes an even address from the remaining bits. for hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. this is to be certain that valid data is available in the bdm shift register, ready to be s hifted out. for hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the bdm waits for a free cycle before stealing a cycle. for bdm firmware read commands, the external host sh ould wait at least 48 bus clock cycles after se nding the command opcode and before attempting to obtain the read da ta. the 48 cycle wait allows enough time for the requested data to be made available in the bdm shift register, ready to be shifted out. for bdm firmware write commands, the extern al host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the external host should wait for at least for 76 bus clock cycles after a trace1 or go command before starting any new serial command. this is to allow the cpu to exit gracefully from t he standard bdm firmware lookup table and resume execution of the user code. disturbing the bdm shift regist er prematurely may adversely affect the exit from the standard bdm firmware lookup table. note if the bus rate of the target processor is unk nown or could be changing, it is recommended that the ack (acknowledge function) is used to indicate when an operation is complete. when using ack, the delay times are automated. figure 57 represents the bdm command structure. the command blocks illustrate a series of eight bit times starting with a falling edge. the bar across the top of the blocks in dicates that the bkgd line idle s in the high state. the time for an 8-bit command is 8 ? 16 target clock cycles. (172) note: 172. target clock cycles are cycles measured using the tar get mcu?s serial clock rate. see section 4.31.4.6, ?bdm serial interface? and section 4.31.3.2.1, ?bdm status register (bdmsts)? for information on how serial clock rate is selected. figure 57. bdm command structure hardware hardware firmware firmware go, 48-bc bc = bus clock cycles command address 150-bc delay next delay 8 bits at ~16 tc/bit 16 bits at ~16 tc/bit 16 bits at ~16 tc/bit command address data next data read write read write trace command next command data 76-bc delay next command 150-bc delay 36-bc delay command command command command data next command tc = target clock cycles
mm912_634 advance information, rev. 4.0 freescale semiconductor 190 4.31.4.6 bdm serial interface the bdm communicates with external devices serially via the bkg d pin. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the bdm. this clock will be referred to as the target clock in the following explanation. the bdm serial interface uses a clocking scheme in which the external host generates a falling edge on the bkgd pin to indicate the start of each bit time. this falling edge is sent for every bit whether data is transmitted or received. data is transferre d most significant bit (msb) first at 16 target clock cycles per bit. the interface times out if 512 clock cycles occur between fallin g edges from the host. the bkgd pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. it is assumed that there is an external pull-up and that drivers connected to bkgd do not typically drive the high level. since r-c rise time coul d be unacceptably long, the target system and host provide brief driven-high (speed up) pulses to drive bkgd to a logic 1. the source of this speedup pulse is the host for transmit cases and the target for receive cases. the timing for host-to-target is shown in figure 58 and that of target-to-host in figure 59 and figure 60 . all four cases begin when the host drives the bkgd pin low to generate a falling edge. since th e host and target are operating from separate clocks, it c an take the target system up to one full clock cycle to recognize th is edge. the target measures del ays from this perceived start of the bit time while the host measures delays from the point it ac tually drove bkgd low to start t he bit up to one target clock c ycle earlier. synchronization between the host and target is established in this manner at the start of every bit time. figure 58 shows an external host transmitting a logic 1 and transmit ting a logic 0 to the bkgd pin of a target system. the host is asynchronous to the target, so there is up to a one clock- cycle delay from the host-generated falling edge to where the targ et recognizes this edge as the beginning of the bit time. ten ta rget clock cycles later, the target senses the bit level on the bk gd pin. internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edg e for a logic 1 transmission. since the host drives the high speedup pulses in these two ca ses, the rising edges look like digitally driven signals. figure 58. bdm host-to-tar get serial bit timing the receive cases are more complicated. figure 59 shows the host receiving a logic 1 from the target system. since the host is asynchronous to the target, there is up to one clock-cycle del ay from the host-generated fa lling edge on bkgd to the perceived start of the bit time in the target. the host holds the bkgd pin low long enough for the target to recognize it (at least two t arget clock cycles). the host must release the low drive before the ta rget drives a brief high speedup pulse seven target clock cycle s after the perceived start of the bit time. the host should sample the bit level about 10 target clock cycles after it started t he bit time. target senses bit 10 cycles synchronization uncertainty bdm clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time earliest start of next bit
mm912_634 advance information, rev. 4.0 freescale semiconductor 191 figure 59. bdm targ et-to-host serial bit timing (logic 1) figure 60 shows the host receiving a logic 0 from the target. since t he host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on bkgd to th e start of the bit time as perceived by the target. the hos t initiates the bit time but the target finishes it. since the targ et wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 target clock cycles after starting the bit time. figure 60. bdm targ et-to-host serial bit timing (logic 0) 4.31.4.7 serial interface ha rdware handshake protocol bdm commands that require cpu execution are ultimately treate d at the mcu bus rate. since the bdm clock source can be modified , it is very helpful to provide a handshake protocol in which the host could determine when an issued command is high-impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin bdm clock (target mcu) host drive to bkgd pin target system speedup pulse high-impedance high-impedance earliest start of next bit bdm clock (target mcu) host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target system drive and speedup pulse speedup pulse high-impedance
mm912_634 advance information, rev. 4.0 freescale semiconductor 192 executed by the cpu. . the alte rnative is to always wait the amount of time e qual to the appropriate number of cycles at the slowest possible rate the clock could be running. this sub-section will describe the ha rdware handshake protocol. the hardware handshake protocol signals to the host controller when an issued comm and was successfully executed by the target. this protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the bkgd pin. th is pulse is generated by the target mcu when a command, i ssued by the host, has been successfully executed (see figure 61 ). this pulse is referred to as the ack pulse. after the ack pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if t he last command was a write command or a control command (background, go, go_until(171) or trace1). the ack pulse is not issued earlier than 32 serial clock cycles after the bdm command was issued. the end of the bdm command is assumed to be the 16th tick of the last bit. this minimum delay assures enough time for the host to perceive the ack pulse. note also that, there is no upper limit for the delay between the command and the related ack pulse, since t he command execution depends upon the cpu bus, which in some cases could be very slow due to long accesses taking place.this protocol allows a great flexibility for the pod designers, since it does not r ely on any accurate time measurement or short response time to any event in the serial communication. figure 61. target a cknowledge pulse (ack) note if the ack pulse was issued by the target, the host assumes the previous command was executed. if the cpu enters stop prior to exec uting a hardware command, the ack pulse will not be issued meaning that the bdm co mmand was not executed. after entering stop mode, the bdm command is no longer pending. figure 62 shows the ack handshake protocol in a command level timing diagram. the read_byte instruction is used as an example. first, the 8-bit instruct ion opcode is sent by the host, followed by the address of the memory location to be read. th e target bdm decodes the instruction. a bus cycle is grabbed (f ree or stolen) by the bdm and it executes the read_byte operation. having retrieved the data, the bdm issues an ack pulse to the host controller, indicating that the addressed byte is ready to be retrieved. after detecting the ac k pulse, the host initiates the byte retrieva l process. note that data is sent in the form of a word and the host needs to determine which is the appro priate byte based on whether the address was odd or even. figure 62. handshake protocol at the command level 16 cycles bdm clock (target mcu) target transmits ack pulse high-impedance bkgd pin minimum delay from the bdm command 32 cycles earliest start of next bit speedup pulse 16th tick of the last command bit high-impedance read_byte bdm issues the bkgd pin byte address bdm executes the read_byte command host target host ta r g e t bdm decodes the command ack pulse (out of scale) host target (2) bytes are retrieved new bdm command
mm912_634 advance information, rev. 4.0 freescale semiconductor 193 differently from the normal bit transfer (w here the host initiates the transmission), the serial interface ack handshake pulse is initiated by the target mcu by issuing a negative edge on the bkgd pin. the hardware handshake protocol in figure 61 specifies the timing when the bkgd pin is being driven, so the host should fo llow this timing constraint in order to avoid the risk of an electrical conflict on the bkgd pin. note the only place the bkgd pin can hav e an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). other ?highs? are pulled rather than driven. however, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. the ack handshake protocol does not support nested ack pulses. if a bdm command is not acknowledge by an ack pulse, the host needs to abort the pending comm and first in order to be able to issue a new bdm command. when the cpu enters stop while the host issues a hardware command (e.g., write_byte), the target discards the incoming command due to the stop being detected. therefor e, the command is not acknowledged by the target, which means that the ack pulse will not be issued in this case. after a certain time the host (not aware of stop) should decide to abort any possible pending ack pulse in order to be sure a new command can be issued. therefore, the prot ocol provides a mechanism in which a command, and its corresponding ack, can be aborted. note the ack pulse does not provide a timeout. this means for the go_until(171) command that it can not be distinguished if a stop has been executed (command discarded and ack not issued) or if the ?until? condition (bdm active) is just not reached yet. hence in any case where the ack pulse of a command is not issued the possible pending command should be aborted before issuing a new co mmand. see the handshake abort procedure described in section 4.31.4.8, ?hardware handshake abort procedure? . 4.31.4.8 hardware handshake abort procedure the abort procedure is based on the sync command. in order to abort a command, which had not issued the corresponding ack pulse, the host controller s hould generate a low pulse in the bkgd pin by driving it low for at least 128 serial clock cycl es and then driving it high for one serial clock cycle, providing a speedup pulse.by detecting this long low pulse in the bkgd pin , the target executes t he sync protocol, see section 4.31.4.9, ?sync ? re quest timed reference pulse? , and assumes that the pending command and therefore the rela ted ack pulse, are being aborted. theref ore, after the sync protocol has been completed the host is free to issue new bdm commands. for bdm firmware read or write commands it can not be guaranteed that the pending command is a borted when issuing a sync before the corresponding ack pulse. there is a short latency time from the time the read or write access begins un til it is finished and the corresponding ack pulse is issued. the latency time depends on the firmware read or write command that is issued and on the selected bus clock rate. when the sync command starts during this latency time the read or write command will not be aborted, but the corresponding ack pulse will be aborted. a pending go, trace1 or go_until(1 71) command can not be aborted. only the corresponding ack pulse can be aborted by the sync command. although it is not recommended, the host could abort a pending bdm command by issuing a low pulse in the bkgd pin shorter than 128 serial clock cycles, which will not be interpreted as the sync command. the ack is actually aborted when a negative edge is perceived by the target in the bkgd pin. the short a bort pulse should have at least 4 clock cycles keeping the bkgd pin low, in order to allow the negative edge to be detected by the target.in this case, the tar get will not execute the sync pr otocol but the pending command will be aborted along with the ack puls e. the potential problem with this abort procedure is when there is a conflict between the ack pulse and the short abort puls e. in this case, the target may not perceive the abort pulse. the worst case is when the pending command is a read command (i.e., read_byte). if the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. in this case, host and target will run ou t of synchronism. however, if t he command to be aborted is not a read command the short abort pulse could be used. after a co mmand is aborted the target as sumes the next negative edge, after the abort pulse, is the first bit of a new bdm command. note the details about the short abort pulse are being provided only as a reference for the reader to better understand the bdm internal behavior. it is not recommended that this procedure be used in a real application. since the host knows the target serial clock frequency, the sync command (used to abort a command) does not need to consider the lower possible target frequency. in this case, the host could issue a sync very close to the 128 serial clock cycles length .
mm912_634 advance information, rev. 4.0 freescale semiconductor 194 providing a small overhead on the pulse leng th in order to assure the sync pulse will not be misinterpreted by the target. see section 4.31.4.9, ?sync ? request timed reference pulse? . figure 63 shows a sync command being issued after a read_byte, which aborts the read_byte command. note that, after the command is aborted a new command c ould be issued by the host computer. figure 63. ack abort proced ure at the command level note figure 63 does not represent the signals in a true timing scale figure 64 shows a conflict between the ack pulse and the sync reques t pulse. this conflict coul d occur if a pod device is connected to the target bkgd pin and the ta rget is already in debug active mode. cons ider that the target cpu is executing a pending bdm command at the exact moment the pod is being connected to the bkgd pi n. in this case, an ack pulse is issued along with the sync command. in this case, there is an electr ical conflict between the ack speedup pulse and the sync pulse. since this is not a probable situation, the prot ocol does not prevent th is conflict from happening. figure 64. ack pulse and sync request conflict note this information is being provided so that the mcu integrator will be aware that such a conflict could occur. the hardware handshake protocol is enabled by the ack_enabl e and disabled by the ack_disable bdm commands. this provides backwards compatibilit y with the existing pod devices which are not able to execute the hardware handshake protocol. it also allows for new pod devices, that support the hardware handshake protocol, to freely communicate with the target device. if desired, without the need for waiting for the ack pulse. the commands are described as follows: read_byte read_status bkgd pin memory address new bdm command new bdm command host target host target host target sync response from the target (out of scale) bdm decode and starts to execute the read_byte command read_byte cmd is aborted by the sync request (out of scale) bdm clock (target mcu) target mcu drives to bkgd pin bkgd pin 16 cycles speedup pulse high-impedance host drives sync to bkgd pin ack pulse host sync request pulse at least 128 cycles electrical conflict host and target drive to bkgd pin
mm912_634 advance information, rev. 4.0 freescale semiconductor 195 ? ack_enable ? enables the hardware handshake protoc ol. the target will issue the ack pulse when a cpu command is executed by the cpu. the ack_enable co mmand itself also has the ack pulse as a response. ? ack_disable ? disables the ack pulse protocol. in this case, the host needs to use the wo rst case delay time at the appropriate places in the protocol. the default state of the bdm after reset is hardware handshake protocol disabled. all the read commands will ack (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the bkgd serial pin. all the write commands will ack (if enabl ed) after the data has been received by the bdm through the bkgd serial pin and when the data bus cycle is complete. see section 4.31.4.3, ?bdm hardware commands? and section 4.31.4.4, ?standard bdm firmware commands? for more information on the bdm commands. the ack_enable sends an ack pulse when the command has been co mpleted. this feature coul d be used by the host to evaluate if the target supports the hardware handshake protocol. if an ack pulse is issued in response to this command, the hos t knows that the target supports the hardware handshake protocol. if the target does not support the hardware handshake protocol the ack pulse is not issued. in this case, the ack_enable comma nd is ignored by the target since it is not recognized as a valid command. the background command issues an ack pulse when the cpu changes from normal to background mode. the ack pulse related to this command could be aborted using the sync command. the go command issues an ack pulse when the cpu exits from background mode. the ack pulse related to this command could be aborted using the sync command. the go_until(171) command is equivalent to a go command with exception that the ack pulse, in this case, is issued when the cpu enters into background mode. this command is an alternative to the go command and should be used when the host wants to trace if a breakpoint match occurs and causes the cpu to enter active background mode. note that the ack is issued whenever the cpu enters bdm, which could be caused by a breakpoint match or by a bgnd instruction being executed. the ack pulse related to this command could be aborted using the sync command. the trace1 command has the related ack pulse issued when th e cpu enters background active mode after one instruction of the application program is executed. the ack pulse relat ed to this command could be aborted using the sync command. 4.31.4.9 sync ? request timed reference pulse the sync command is unlike other bdm commands because the host does not necessarily know the correct communication speed to use for bdm communications until after it has analyzed the response to the sync command. to issue a sync command, the host should perform the following steps: 1. drive the bkgd pin low for at least 128 cycles at th e lowest possible bdm serial communication frequency 2. drive bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. remove all drive to the bkgd pin so it reverts to high impedance. 4. listen to the bkgd pin for the sync response pulse. upon detecting the sync request from the hos t, the target performs the following steps: 1. discards any incomplete command received or bit retrieved. 2. waits for bkgd to return to a logic one. 3. delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. drives bkgd low for 128 cycles at the cu rrent bdm serial communication frequency. 5. drives a one-cycle high speedup pulse to force a fast rise time on bkgd. 6. removes all drive to the bkgd pin so it reverts to high impedance. the host measures the low time of this 128 cycle sync res ponse pulse and determines the correct speed for subsequent bdm communications. typically, the host can determine the correct co mmunication speed within a few pe rcent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. as soon as the sync request is detected by the target, any pa rtially received command or bit retrieved is discarded. this is referred to as a soft-reset, equivalent to a time-out in the serial communication. af ter the sync response, the target will con sider the next negative edge (issued by the host) as the star t of a new bdm command or the start of new sync request. another use of the sync command pulse is to abort a pending ac k pulse. the behavior is exactly the same as in a regular sync command. note that one of the possible causes for a comm and to not be acknowledged by the target is a host-target synchronization problem. in this case, the command may not have been understood by the target and so an ack response pulse will not be issued.
mm912_634 advance information, rev. 4.0 freescale semiconductor 196 4.31.4.10 instruction tracing when a trace1 command is issued to the bdm in active bdm, t he cpu exits the standard bdm firmware and executes a single instruction in the user code. once this has occurred, the cpu is forced to return to the standard bdm firmware and the bdm is active and ready to receive a new command. if the trace1 comma nd is issued again, the next us er instruction will be executed. this facilitates stepping or tracing throu gh the user code one instruction at a time. if an interrupt is pending when a trace1 command is issued, the interrupt stacking op eration occurs but no user instruction is executed. once back in standard bdm firmware execution, the program counter points to the first instruction in the interrupt service routine. be aware when tracing through the user co de that the execution of the user code is done step by step but peripherals are free running. hence possible timing relations between cpu code exec ution and occurrence of events of other peripherals no longer exist. do not trace the cpu instruction bgnd used for soft breakpoints. tracing over the bg nd instruction will result in a return addr ess pointing to bdm firmware address space. when tracing through user code which contains stop instructi ons the following will happen when the stop instruction is traced: the cpu enters stop mode and the trace1 command can not be finished before leaving the low power mode. this is the case because bdm active mode can not be entered af ter cpu executed the stop instruction. however all bdm hardware commands except the background command are operat ional after tracing a stop instruction and still being in stop mode. if system stop mode is entered (all bus masters are in st op mode) no bdm command is operational. as soon as stop mode is exited the cpu enters bdm acti ve mode and the saved pc value points to the entry of the corresponding interrupt service routine. in case the handshake feature is enabled the correspo nding ack pulse of the trace1 command will be discarded when tracing a stop instruction. hence there is no ack pulse when bdm active mode is entered as part of the trace1 command after cpu exited from stop mode. all valid co mmands sent during cpu being in stop mode or after cpu exited from stop mode will have an ack pulse. the handshake f eature becomes disabled onl y when system stop mode has been reached. hence after a system stop mode the handshake feature must be enabled again by sending the ack_enable command. 4.31.4.11 serial communication timeout the host initiates a host-to-target serial transmission by generat ing a falling edge on the bkgd pin. if bkgd is kept low for m ore than 128 target clock cycles, the target understands that a sync command was issued. in this case, the target will keep waiting for a rising edge on bkgd in order to answer the sync request pulse. if the rising edge is not detected, the target will keep waiting forever without any timeout limit. consider now the case where the host returns bkgd to logic one be fore 128 cycles. this is interpreted as a valid bit transmissi on, and not as a sync request. the target will keep waiting for anot her falling edge marking the start of a new bit. if, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the curren t command is discarded without affecting memory or the operating mode of the mcu. this is referred to as a soft-reset. if a read command is issued but the data is not retrieved with in 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. the data is not available for retrieva l after the timeout has occurred. this is the expected behavio r if the handshake protocol is not enabled. in order to allow the data to be retrieved even with a large clock frequency mismatch (between bdm and cpu) when the hardwar e handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. therefore, the ho st could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. however, once the handshake pulse (ack pulse) is issued, the ti meout feature is re-activated, meaning that the target wil l time out after 512 clock cycles. therefore, the hos t needs to retrieve the data within a 512 seria l clock cycles time frame after the ack pulse had been issued. after th at period, the read command is discarded and the data is no longer available for retrieval. any negative edge in the bkgd pin after the timeout period is considered to be a new command or a sync request. note that whenever a partially issued comm and, or partially retrieved data, has occurr ed the timeout in the serial communicatio n is active. this means that if a time frame higher than 512 seri al clock cycles is observed betw een two consecutive negative edg es and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarde d. the next negative edge in the bkgd pi n, after a soft-reset has occurred, is considered by the target as the start of a new bdm command, or the start of a sync request pulse.
mm912_634 advance information, rev. 4.0 freescale semiconductor 197 4.32 s12s debug module (s12sdbgv2) 4.32.1 introduction the s12sdbg module provides an on-chip trace buffer with fl exible triggering capability to allow non-intrusive debug of application software. the s12sdbg module is optimized for s12scpu debugging. typically the s12sdbg module is used in conjunction with th e s12sbdm module, whereby the user configures the s12sdbg module for a debugging session over the bdm interface. once configured the s12sdbg module is armed and the device leaves bdm returning control to the user program, which is then m onitored by the s12sdbg module . alternatively the s12sdbg module can be configured over a seri al interface using swi routines. 4.32.1.1 glossary of terms cof: change of flow. change in the program flow due to a conditional branch, indexed jump or interrupt. bdm: background debug mode s12sbdm: background debug module dug: device user guide, describing the features of the device into which the dbg is integrated. word: 16 bit data entity data line: 20 bit data entity cpu: s12scpu module dbg: s12sdbg module por: power on reset tag: tags can be attached to cpu opcodes as they enter the instruction pipe. if the tagged opcode reaches the execution stage a tag hit occurs. 4.32.1.2 overview the comparators monitor the bus activity of the cpu module. a ma tch can initiate a state sequenc er transition. on a transition to the final state, bus tracing is trigge red and/or a breakpoi nt can be generated. independent of comparator matches a transition to final stat e with associated tracing and breakpoint can be triggered immediately by writing to the trig control bit. the trace buffer is visible through a 2-byte window in the re gister address map and can be read out using standard 16-bit word reads. tracing is disabled w hen the mcu system is secured. 4.32.1.3 features ? three comparators (a, b and c) ? comparators a compares the full address bus and full 16-bit data bus ? comparator a features a data bus mask register ? comparators b and c compare the full address bus only ? each comparator features selectio n of read or write access cycles ? comparator b allows selection of byte or word access cycles ? comparator matches can initiate state sequencer transitions ? three comparator modes ? simple address/data comparator match mode ? inside address range mode, addmin ? address ?? addmax ? outside address range match mode, address ?? addmin ? or address ? addmax ? two types of matches ? tagged ? this matches just before a specific instruction begins execution ? force ? this is valid on the first in struction boundary after a match occurs ? two types of breakpoints ? cpu breakpoint entering bdm on breakpoint (bdm) ? cpu breakpoint executing swi on breakpoint (swi) ? trigger mode independent of comparators ? trig immediate software trigger
mm912_634 advance information, rev. 4.0 freescale semiconductor 198 ? four trace modes ? normal: change of flow (cof) pc information is stored (see section 4.32.4.5.2. 1, ?normal mode ) for change of flow definition. ? loop1: same as normal but inhibits co nsecutive duplicate source address entries ? detail: address and data for all cycles except free cycles and opcod e fetches are stored ? compressed pure pc: all program counter addresses are stored ? 4-stage state sequencer for trace buffer control ? tracing session trigger linked to final state of state sequencer ? begin and end alignment of tracing to trigger 4.32.1.4 modes of operation the dbg module can be used in all mcu functional modes. during bdm hardware accesses and whilst the bdm module is ac tive, cpu monitoring is disabled. when the cpu enters active bdm mode through a background command, the db g module, if already a rmed, remains armed. the dbg module tracing is disabled if the mcu is secure, however, breakpoints can still be generated 4.32.1.5 block diagram figure 65. debug module block diagram table 268. mode dependent restriction summary bdm enable bdm active mcu secure comparator matches enabled breakpoints possible tagging possible tracing possible x x 1 yes yes yes no 0 0 0 yes only swi yes yes 0 1 0 active bdm not possible when not enabled 1 0 0 yes yes yes yes 110 no no no no cpu bus trace buffer bus interface transition match0 state comparator b comparator c comparator a state sequencer match1 match2 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control trigger tag & match control logic tags taghits state to cpu
mm912_634 advance information, rev. 4.0 freescale semiconductor 199 4.32.2 external signal description there are no external signals associated with this module. 4.32.3 memory map and registers 4.32.3.1 module memory map a summary of the registers associated with the dbg sub-block is shown in figure 269 . detailed descriptions of the registers and bits are given in the subsections that follow. table 269. quick reference to dbg registers address name bit 7 6 5 4 3 2 1 bit 0 0x0020 dbgc1 r arm 00 bdm dbgbrk 0 comrv wtrig 0x0021 dbgsr rtbf (173) 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r0 tsource 00 trcmod 0 talign w 0x0023 dbgc2 r000000 abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl rbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w 0x0026 dbgcnt r tbf 0 cnt w 0x0027 dbgscrx r0000 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r00000mc2mc1mc0 w 0x0028 dbgactl r sze sz tag brk rw rwe ndb compe w 0x0028 dbgbctl r sze sz tag brk rw rwe 0 compe w 0x0028 dbgcctl r0 0 tag brk rw rwe 0 compe w 0x0029 dbgxah r000000 bit 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 76 5 4 3 2 1bit 0 w 0x002c dbgadh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgadl r bit 76 5 4 3 2 1bit 0 w
mm912_634 advance information, rev. 4.0 freescale semiconductor 200 4.32.3.2 register descriptions this section consists of the dbg control and trace buffer register descriptions in addr ess order. each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002f in the dbg module register address map. when arm is set in dbgc1, the only bits in the dbg module registers that can be written are arm, trig, and comrv[1:0] 4.32.3.2.1 debug control register 1 (dbgc1) read: anytime write: bits 7, 1, 0 anytime bit 6 can be written anytime but always reads back as 0. bits 4:3 anytime dbg is not armed. note when disarming the dbg by clearing arm with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, arm = 1 preventing these bits from being written. these bits must be clea red using a second write if required. 0x002e dbgadhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgadlm r bit 76 5 4 3 2 1bit 0 w note: 173. this bit is visible at dbgcnt[7] and dbgsr[7] 174. this represents the contents if the comparator a control register is blended into this address. 175. this represents the contents if the comparator b control register is blended into this address. 176. this represents the contents if the comparator c control register is blended into this address. table 270. debug control register (dbgc1) address: 0x0020 76543210 r arm 00 bdm dbgbrk 0 comrv wtrig reset00000000 = unimplemented or reserved table 269. quick reference to dbg registers address name bit 7 6 5 4 3 2 1 bit 0
mm912_634 advance information, rev. 4.0 freescale semiconductor 201 4.32.3.2.2 debug status register (dbgsr) read: anytime write: never table 271. dbgc1 field descriptions field description 7 arm arm bit ? the arm bit controls whether the dbg module is armed. this bit can be set and cleared by user software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. on setting this bit the state sequencer enters state1. 0 debugger disarmed 1 debugger armed 6 trig immediate trigger request bit ? this bit when written to 1 requests an immediate trigger independent of state sequencer status. when tracing is complete a forced breakpoint may be generated depending upon dbgbrk and bdm bit settings. this bit always reads back a 0. writing a 0 to this bit has no effec t. if the dbgtcr_tsource bit is cl ear no tracing is carried out. if tracing has already commenced using begin trigger alignment, it continues until the end of the tracing session as defined by the talign bit, thus trig has no affect. in secure mode trac ing is disabled and writing to th is bit cannot initiate a tracin g session. the session is ended by setting trig and arm simultaneously. 0 do not trigger until the state sequencer enters the final state. 1 trigger immediately 4 bdm background debug mode enable ? this bit determines if a breakpoint caus es the system to enter background debug mode (bdm) or initiate a software interrupt (swi). if this bit is set but the bdm is not enabled by the enbdm bit in the bdm module, then breakpoints default to swi. 0 breakpoint to software interrupt if bdm inactive. otherwise no breakpoint. 1 breakpoint to bdm, if bdm enabled. otherwise breakpoint to swi 3 dbgbrk s12sdbg breakpoint enable bit ? the dbgbrk bit controls whether the de bugger will request a breakpoint on reaching the state sequencer final state. if tracing is enabled, the breakpoint is generated on completion of the tracing session. if tr acing is not enabled, the breakpoint is generated immediately. 0 no breakpoint generated 1 breakpoint generated 1?0 comrv comparator register visibility bits ? these bits determine which bank of comparator register is visible in the 8-byte window of the s12sdbg module address map, located between 0x0028 to 0x002f. furthermore these bits determine which register is visible at the address 0x0027. see table 272 . table 272. comrv encoding comrv visible comparator visible register at 0x0027 00 comparator a dbgscr1 01 comparator b dbgscr2 10 comparator c dbgscr3 11 none dbgmfr table 273. debug status register (dbgsr) address: 0x0021 76543210 r tbf 0 0 0 0 ssf2 ssf1 ssf0 w reset por ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 202 4.32.3.2.3 debug trace control register (dbgtcr) read: anytime write: bit 6 only when dbg is neither secure nor armed.bits 3,2,0 anytime the module is disarmed. table 274. dbgsr field descriptions field description 7 tbf trace buffer full ? the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of db gcnt bits. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit this bit is also visible at dbgcnt[7] 2?0 ssf[2:0] state sequencer flag bits ? the ssf bits indicate in which state the state sequencer is currently in. during a debug session on each transition to a new state these bits are updated. if the debug session is ended by software clearing the arm bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. if a debug session is ended by an internal event, then the state sequencer returns to state0 and t hese bits are cleared to indicate that state0 was entered durin g the session. on arming the module the state sequencer enters state1 and these bits are forced to ssf[2:0] = 001. see ta b l e 2 7 5 . table 275. ssf[2:0] ? state sequence flag bit encoding ssf[2:0] current state 000 state0 (disarmed) 001 state1 010 state2 011 state3 100 final state 101,110,111 reserved table 276. debug trace control register (dbgtcr) address: 0x0022 76543210 r0 tsource 00 trcmod 0 talign w reset00000000 table 277. dbgtcr field descriptions field description 6 tsource trace source control bit ? the tsource bit enables a tracing session giv en a trigger condition. if the mcu system is secured, this bit cannot be se t and tracing is inhibited. this bit must be set to read the trace buffer. 0 debug session without tracing requested 1 debug session with tracing requested 3?2 trcmod trace mode bits ? see section 4.32.4.5.2, ?trace modes for detailed trace mode descript ions. in normal mode, change of flow information is stored. in loop1 mode, change of flow info rmation is stored but redundant entries into trace memory are inhibited. in detail mode, address and data for all memory and regi ster accesses is stored. in compressed pure pc mode the program counter value for each instruction executed is stored. see table 278 . 0 talign trigger align bit ? this bit controls whether the trigger is a ligned to the beginning or end of a tracing session. 0 trigger at end of stored data 1 trigger before storing data
mm912_634 advance information, rev. 4.0 freescale semiconductor 203 4.32.3.2.4 debug contro l register2 (dbgc2) read: anytime write: anytime the module is disarmed. this register configures the comparators for range matching. 4.32.3.2.5 debug trace buffe r register (dbgtbh:dbgtbl) read: only when unlocked and unsecured and not armed and tsource set. write: aligned word writes when disarmed unlock the trace buff er for reading but do not affe ct trace buffer contents. table 278. trcmod trace mode bit encoding trcmod description 00 normal 01 loop1 10 detail 11 compressed pure pc table 279. debug control register2 (dbgc2) address: 0x0023 76543210 r000000 abcm w reset00000000 = unimplemented or reserved table 280. dbgc2 field descriptions field description 1?0 abcm[1:0] a and b comparator match control ? these bits determine the a and b comparator match mapping as described in table 281 . table 281. abcm encoding abcm description 00 match0 mapped to comparator a match: match1 mapped to comparator b match. 01 match 0 mapped to comparator a/b inside range: match1 disabled. 10 match 0 mapped to comparator a/b outside range: match1 disabled. 11 reserved (177) note: 177. currently defaults to comparator a, comparator b disabled table 282. debug trace buffer register (dbgtb) address: 0x0024, 0x0025 1514131211109876543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bi t 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w porxxxxxxxx xxxxxxxx other resets ????????? ???????
mm912_634 advance information, rev. 4.0 freescale semiconductor 204 4.32.3.2.6 debug count register (dbgcnt) read: anytime write: never table 283. dbgtb field descriptions field description 15?0 bit[15:0] trace buffer data bits ? the trace buffer register is a window through wh ich the 20-bit wide data lines of the trace buffer may be read 16 bits at a time. each vali d read of dbgtb increments an internal trace buffer pointer which points to the next address to be read. when the arm bit is se t the trace buffer is locked to prevent r eading. the trace buffer can only be unlocke d for reading by writing to dbgtb with an aligned word write wh en the module is disarmed. the dbgtb register can be read only as an aligned word, any byte reads or misaligned access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. similarl y reads while the debugger is armed or with the tsource bit clear, return 0 and do not affect the trace buffer pointer. the por state is undefined. other resets do not affect the trace bu ffer contents. table 284. debug count register (dbgcnt) address: 0x0026 76543210 r tbf 0 cnt w reset por ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 = unimplemented or reserved table 285. dbgcnt field descriptions field description 7 tbf trace buffer full ? the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of db gcnt bits. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit this bit is also visible at dbgsr[7] 5?0 cnt[5:0] count value ? the cnt bits indicate the number of valid data 20-bit data lines stored in the trace buffer. table 286 shows the correlation between the cnt bits and the number of valid data lines in the trace buffer. when the cnt rolls over to zero, the tbf bit in dbgsr is set and incrementi ng of cnt will continue in end-trigger m ode. the dbgcnt register is cleared when arm in dbgc1 is written to a one. the dbgcnt register is clea red by power-on-reset initializati on but is not cleared by other system resets. thus should a reset occur during a debug session, the dbgcnt register still indicates after the reset, the number of valid trace buffer entries stored before the reset oc curred. the dbgcnt register is not decremented when reading from the trace buffer. table 286. cnt decoding table tbf cnt[5:0] description 0 000000 no data valid 0 000001 000010 000100 000110 ? 111111 1 line valid 2 lines valid 4 lines valid 6 lines valid ? 63 lines valid
mm912_634 advance information, rev. 4.0 freescale semiconductor 205 4.32.3.2.7 debug stat e control registers there is a dedicated control register for ea ch of the state sequencer states 1 to 3 th at determines if transitions from that st ate are allowed, depending upon comparator matches or tag hits, and de fines the next state for the state sequencer following a match. the three debug state control registers are lo cated at the same address in the register address map (0 x0027). each register can be accessed using the comrv bits in dbgc1 to blend in the required register. the comrv = 11 value blends in the match flag register (dbgmfr). 4.32.3.2.7.1 debug state control register 1 (dbgscr1) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and dbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 00. the state control regi ster 1 selects the ta rgeted next state whil st in state1. the matches refer to the match channels of the comparator match control logic as depicted in figure 65 and described in 4.32.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. 1 000000 64 lines valid; if using begin trigger alignment, arm bit will be cleared and the tracing session ends. 1 000001 ? ? 111110 64 lines valid, oldest data has been overwritten by most recent data table 287. state control register access encoding comrv visible state control register 00 dbgscr1 01 dbgscr2 10 dbgscr3 11 dbgmfr table 288. debug state control register 1 (dbgscr1) address: 0x0027 76543210 r0 0 0 0 sc3 sc2 sc1 sc0 w reset00000000 = unimplemented or reserved table 289. dbgscr1 field descriptions field description 3?0 sc[3:0] these bits select the targeted next state whilst in state1, based upon the match event. table 290. state1 sequencer next state selection sc[3:0] description (unspecified matches have no effect) 0000 any match to final state 0001 match1 to state3 0010 match2 to state2 table 286. cnt decoding table tbf cnt[5:0] description
mm912_634 advance information, rev. 4.0 freescale semiconductor 206 the priorities described in table 323 dictate that in the case of simultaneous matc hes, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). thus with sc[3:0]=1101 a simultaneous match0/match1 transitions to final state. 4.32.3.2.7.2 debug state control register 2 (dbgscr2) read: if comrv[1:0] = 01 write: if comrv[1:0] = 01 and dbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 01. the state control regi ster 2 selects the ta rgeted next state whil st in state2. the matches refer to the match channels of the comparator match control logic as depicted in figure 65 and described in section 4.32.3.2.8.1, ?debug compar ator control register (dbgxctl) . comparators must be enabled by setting the comparator enable bit in the asso ciated dbgxctl control register. 0011 match1 to state2 0100 match0 to state2....... match1 to state3 0101 match1 to state3.........match0 to final state 0110 match0 to state2....... match2 to state3 0111 either match0 or match1 to state2 1000 reserved 1001 match0 to state3 1010 reserved 1011 reserved 1100 reserved 1101 either match0 or match2 to final state........match1 to state2 1110 reserved 1111 reserved table 291. debug state control register 2 (dbgscr2) address: 0x0027 76543210 r0 0 0 0 sc3 sc2 sc1 sc0 w reset00000000 = unimplemented or reserved table 292. dbgscr2 field descriptions field description 3?0 sc[3:0] these bits select the targeted next state whilst in state2, based upon the match event. table 293. state2 ?sequencer next state selection sc[3:0] description (unspecified matches have no effect) 0000 match0 to state1....... match2 to state3. 0001 match1 to state3 0010 match2 to state3 table 290. state1 sequencer next state selection sc[3:0] description (unspecified matches have no effect)
mm912_634 advance information, rev. 4.0 freescale semiconductor 207 the priorities described in table 323 dictate that in the case of simultaneous matc hes, a match leading to final state has priority followed by the match on the lower channel number (0,1,2) 4.32.3.2.7.3 debug state control register 3 (dbgscr3) read: if comrv[1:0] = 10 write: if comrv[1:0] = 10 and dbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 10. the state control regi ster three selects the targeted next state whilst in state3. the matches refer to the match channels of the comparator match control logic as depicted in figure 65 and described in section 4.32.3.2.8.1, ?debug compar ator control register (dbgxctl) . comparators must be enabled by setting the comparator enable bit in the asso ciated dbgxctl control register. 0011 match1 to state3....... match0 final state 0100 match1 to state1....... match2 to state3. 0101 match2 to final state 0110 match2 to state1..... match0 to final state 0111 either match0 or match1 to final state 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 either match0 or match1 to final state........match2 to state3 1101 reserved 1110 reserved 1111 either match0 or match1 to final state........match2 to state1 table 294. debug state control register 3 (dbgscr3) address: 0x0027 76543210 r0 0 0 0 sc3 sc2 sc1 sc0 w reset00000000 = unimplemented or reserved table 295. dbgscr3 field descriptions field description 3?0 sc[3:0] these bits select the targeted next state whilst in state3, based upon the match event. table 296. state3 ? sequencer next state selection sc[3:0] description (unspecified matches have no effect) 0000 match0 to state1 0001 match2 to state2........ match1 to final state 0010 match0 to final state....... match1 to state1 0011 match1 to final state....... match2 to state1 table 293. state2 ?sequencer next state selection sc[3:0] description (unspecified matches have no effect)
mm912_634 advance information, rev. 4.0 freescale semiconductor 208 the priorities described in table 323 dictate that in the case of simultaneous matc hes, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). 4.32.3.2.7.4 debug match flag register (dbgmfr) read: if comrv[1:0] = 11 write: never dbgmfr is visible at 0x0027 only with comrv[ 1:0] = 11. it features 3 flag bits each mapped directly to a channel. should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the arm bit. thus the contents ar e retained after a debug session for evaluation purposes. these flags cannot be cleared by software, they are cleared only when arming the module. a set flag does not inhibit the setting of o ther flags. once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag. 4.32.3.2.8 comparator re gister descriptions each comparator has a bank of registers that are visible thro ugh an 8-byte window in the dbg module register address map. comparator a consists of 8 register bytes (3 address bus compar e registers, two data bus compar e registers, two data bus mask registers and a control register). comparat or b consists of four register bytes (t hree address bus compare registers and a cont rol register). comparator c consists of fo ur register bytes (three address bus comp are registers and a control register). each set of comparator registers can be accessed using the co mrv bits in the dbgc1 register . unimplemented registers (e.g. comparator b data bus and data bus masking) read as zero and cannot be written. the control regist er for comparator b differs from those of comparators a and c. 0100 match1 to state2 0101 match1 to final state 0110 match2 to state2........ match0 to final state 0111 match0 to final state 1000 reserved 1001 reserved 1010 either match1 or match2 to state1....... match0 to final state 1011 reserved 1100 reserved 1101 either match1 or match2 to final state....... match0 to state1 1110 match0 to state2....... match2 to final state 1111 reserved table 297. debug match flag register (dbgmfr) address: 0x0027 76543210 r 0 0 0 0 0 mc2 mc1 mc0 w reset00000000 = unimplemented or reserved table 298. comparator register layout 0x0028 control read/write comparators a,b and c 0x0029 address high read/write comparators a,b and c 0x002a address medium read/write comparators a,b and c table 296. state3 ? sequencer next state selection sc[3:0] description (unspecified matches have no effect)
mm912_634 advance information, rev. 4.0 freescale semiconductor 209 4.32.3.2.8.1 debug comparator control regist er (dbgxctl) the contents of this register bits 7 and 6 differ depending u pon which comparator registers are visible in the 8-byte window of the dbg module register address map. read: dbgactl if comrv[1:0] = 00 dbgbctl if comrv[1:0] = 01 dbgcctl if comrv[1:0] = 10 write: dbgactl if comrv[1: 0] = 00 and dbg not armed dbgbctl if comrv[1:0] = 01 and dbg not armed dbgcctl if comrv[1:0] = 10 and dbg not armed 0x002b address low read/write comparators a,b and c 0x002c data high comparator read/write comparator a only 0x002d data low comparator read/write comparator a only 0x002e data high mask read/write comparator a only 0x002f data low mask read/write comparator a only table 299. debug comparator contro l register dbgactl (comparator a) address: 0x0028 76543210 r sze sz tag brk rw rwe ndb compe w reset00000000 = unimplemented or reserved table 300. debug comparator contro l register dbgbctl (comparator b) address: 0x0028 76543210 r sze sz tag brk rw rwe 0 compe w reset00000000 = unimplemented or reserved table 301. debug comparator contro l register dbgcctl (comparator c) address: 0x0028 76543210 r0 0 tag brk rw rwe 0 compe w reset00000000 = unimplemented or reserved table 298. comparator register layout
mm912_634 advance information, rev. 4.0 freescale semiconductor 210 table 303 shows the effect for rwe and rw on the comparison cond itions. these bits are ignored if the corresponding tag bit is set since the match occurs based on the tagged opco de reaching the execution stag e of the instruction queue. table 302. dbgxctl field descriptions field description 7 sze (comparators a and b) size comparator enable bit ? the sze bit controls whether access size comparison is enabled for the associated comparator. this bit is ignored if the tag bit in the same register is set. 0 word/byte access size is not used in comparison 1 word/byte access size is used in comparison 6 sz (comparators a and b) size comparator value bit ? the sz bit selects either word or byte access size in comparison for the associated comparator. this bit is ignored if the sze bit is clear ed or if the tag bit in the same register is set. 0 word access size is compared 1 byte access size is compared 5 tag tag select ? this bit controls whether the comp arator match has immediate effect, causing an immediate state sequencer transition or tag the opcode at the matched address. tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 allow state sequencer trans ition immediately on match 1 on match, tag the opcode. if the opcode is about to be executed allow a st ate sequencer transition 4 brk break ? this bit controls whether a comparator match term inates a debug session immediately, independent of state sequencer state. to generate an immediate breakpoint t he module breakpoints must be enabled using the dbgc1 bit dbgbrk. 0 the debug session termination is dependent upon the state sequencer and trigger conditions. 1 a match on this channel terminates the debug session immedi ately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 rw read/write comparator value bit ? the rw bit controls whether read or wr ite is used in compare for the associated comparator. the rw bit is not used if rwe = 0. this bit is ignored if the tag bit in the same register is set. 0 write cycle is match ed1 read cycle is matched 2 rwe read/write enable bit ? the rwe bit controls whether read or write comparison is enabled for the associated comparator.this bit is ignored if the tag bit in the same register is set 0 read/write is not used in comparison 1 read/write is used in comparison 1 ndb (comparator a) not data bus ? the ndb bit controls whether the match occurs w hen the data bus matches the comparator register value or when the data bus differs from the register value. this bit is ignored if the tag bi t in the same register is set. this bit is only available for comparator a. 0 match on data bus equivalence to comparator register contents 1 match on data bus difference to comparator register contents 0 compe determines if comparator is enabled 0 the comparator is not enabled 1 the comparator is enabled table 303. read or write comparison logic table rwe bit rw bit rw signal comment 0 x 0 rw not used in comparison 0 x 1 rw not used in comparison 1 0 0 write data bus 1 0 1 no match 11 0 no match 1 1 1 read data bus
mm912_634 advance information, rev. 4.0 freescale semiconductor 211 4.32.3.2.8.2 debug comparator ad dress high regi ster (dbgxah) the dbgc1_comrv bits determine which comparator address regi sters are visible in the 8-byte window from 0x0028 to 0x002f as shown in section , ? read: anytime. see ta b l e for visible register encoding. write: if dbg not armed. see table for visible register encoding. 4.32.3.2.8.3 debug comparator address mid register (dbgxam) read: anytime. see ta b l e for visible register encoding. write: if dbg not armed. see table for visible register encoding. table 304. debug comparator ad dress high regi ster (dbgxah) address: 0x0029 76543210 r000000 bit 17 bit 16 w reset00000000 = unimplemented or reserved table 305. comparator address register visibility comrv visible comparator 00 dbgaah, dbgaam, dbgaal 01 dbgbah, dbgbam, dbgbal 10 dbgcah, dbgcam, dbgcal 11 none table 306. dbgxah fi eld descriptions field description 1?0 bit[17:16] comparator address high compare bits ? the comparator address high compare bits control whether the selected comparator compares the address bus bits [17:16] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one table 307. debug comparator address mid register (dbgxam) address: 0x002a 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 table 308. dbgxam field descriptions field description 7?0 bit[15:8] comparator address mid compare bits ? the comparator address mid compare bits control whether the selected comparator compares the address bus bits [15:8] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one
mm912_634 advance information, rev. 4.0 freescale semiconductor 212 4.32.3.2.8.4 debug comparator address low register (dbgxal) read: anytime. see ta b l e for visible register encoding. write: if dbg not armed. see table for visible register encoding. 4.32.3.2.8.5 debug comparator data high register (dbgadh) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and dbg not armed. 4.32.3.2.8.6 debug comparator data low register (dbgadl) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and dbg not armed. table 309. debug comparator address low register (dbgxal) address: 0x002b 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 table 310. dbgxal field descriptions field description 7?0 bits[7:0] comparator address low compare bits ? the comparator address low compare bits control whether the selected comparator compares the address bus bi ts [7:0] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one table 311. debug comparator data high register (dbgadh) address: 0x002c 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 table 312. dbgadh field descriptions field description 7?0 bits[15:8] comparator data high compare bits ? the comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparator a. data bus comparisons are only performed if the tag bit in dbgactl is clear. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one table 313. debug comparator data low register (dbgadl) address: 0x002d 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000
mm912_634 advance information, rev. 4.0 freescale semiconductor 213 4.32.3.2.8.7 debug comparator data high mask register (dbgadhm) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and dbg not armed. 4.32.3.2.8.8 debug comparator da ta low mask register (dbgadlm) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and dbg not armed. table 314. dbgadl field descriptions field description 7?0 bits[7:0] comparator data low compare bits ? the comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logi c one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparator a. data bus comparisons are only performed if the tag bit in dbgactl is clear 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one table 315. debug comparator data high mask register (dbgadhm) address: 0x002e 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset00000000 table 316. dbgadhm field descriptions field description 7?0 bits[15:8] comparator data high mask bits ? the comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. data bus comparisons are only performed if the tag bit in dbgactl is clear 0 do not compare corresponding data bit any va lue of corresponding data bit allows match. 1 compare corresponding data bit table 317. debug comparator da ta low mask register (dbgadlm) address: 0x002f 76543210 r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w reset00000000 table 318. dbgadlm field descriptions field description 7?0 bits[7:0] comparator data low mask bits ? the comparator data low mask bits contro l whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. data bus comparisons are only performed if the tag bit in dbgactl is clear 0 do not compare corresponding data bit. any va lue of corresponding data bit allows match 1 compare corresponding data bit
mm912_634 advance information, rev. 4.0 freescale semiconductor 214 4.32.4 functional description this section provides a complete functional description of the dbg module. if the part is in secure mode, the dbg module can generate breakpoints but tracing is not possible. 4.32.4.1 s12sdb g operation arming the dbg module by setting arm in dbgc1 allows triggerin g the state sequencer, storing of data in the trace buffer and generation of breakpoints to the cpu. the db g module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. the comparators monitor the bus activity of the cpu. all comp arators can be configured to monitor address bus activity. comparator a can also be configured to monitor data bus activity and mask out individual data bus bits during a compare. comparators can be configured to use r/w and word/byte access qualification in the comparison. a match with a comparator register value can initiate a state se quencer transition to another state (see figure 67 ). either forced or tagged matches are possible. using a forced match, a state sequencer transition can occur immediately on a successf ul match of system busses and comparator registers. whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reach es the execution stage of the instruction queue can a state sequencer transition occur. in the case of a transition to final state , bus tracing is triggered and/or a breakpoint can be generated. a state sequencer transition to final state (with associated break point, if enabled) can be initia ted by writing to the trig bi t in the dbgc1 control register. the trace buffer is visible through a 2-byte window in the regi ster address map and must be read out using standard 16-bit word reads. figure 66. dbg overview 4.32.4.2 comparator modes the dbg contains three comparat ors, a, b and c. each comp arator compares th e system address bus with the address stored in dbgxah, dbgxam, and dbgxal. furthermo re, comparator a also compares the data buses to the data stored in dbgadh, dbgadl and allows masking of individual data bus bits. all comparators are disabled in bdm and during bdm accesses. the comparator match control logic (see figure 66 ) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside th e specified range generates a ma tch condition. the comparator configuration is controlled by the control register content s and the range control by the dbgc2 contents. cpu bus trace buffer bus interface transition match0 state comparator b comparator c comparator a state sequencer match1 match2 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control trigger tag & match control logic tags taghits state to cpu
mm912_634 advance information, rev. 4.0 freescale semiconductor 215 a match can initiate a transition to another state sequencer state (see section 4.32.4.4, ?sta te sequence control? ). the comparator control register also allows the type of access to be included in the comp arison through the use of the rwe, rw, sze, and sz bits. the rwe bit controls wh ether read or write comparis on is enabled for the associated comparator and the rw bit selects either a read or write access for a valid match. sim ilarly the sze and sz bits allow the size of access (word or by te) to be considered in the compare. only comparators a and b feature sze and sz. the tag bit in each comparator control r egister is used to determine the match c ondition. by setting tag, the comparator qualifies a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction reaches the cpu execution stage. whilst tagging the rw, rwe, sze, and sz bits and the comparat or data registers are ignored; the comparator address register must be loaded with the exact opcode address. if the tag bit is clear (forced type ma tch) a comparator match is generated w hen the selected address appears on the system address bus. if the selected address is an opcode address, the matc h is generated when the opcode is fetched from the memory, which precedes the instruction exec ution by an indefinite number of cycles due to instruction pipelining. for a comparator matc h of an opcode at an odd address when tag = 0, the corresponding even address must be containe d in the comparator register. thus for an opcode at odd address (n), the co mparator register must contain address (n?1). once a successful comparator match has occurred, the condit ion that caused the original ma tch is not verified again on subsequent matches. thus if a particular data value is verified at a given address, this address may not still contain that dat a value when a subsequent match occurs. match[0, 1, 2] map directly to comparators [a, b, c] respectively, except in range modes (see section 4.32.3.2.4, ?debug control register2 (dbgc2) ). comparator channel priority rules are described in the priority section ( section 4.32.4. 3.4, ?channel priorities) . 4.32.4.2.1 single addre ss comparator match with range comparisons disabled, the match condition is an ex act equivalence of address bus with the value stored in the comparator address registers. further qualification of the type of access (r/w, word/byte) and data bus contents is possible, depending on comparator channel. 4.32.4.2.1.1 comparator c comparator c offers only address and direction (r/w) comparis on. the exact address is compared, thus with the comparator address register loaded with address (n) a word access of addr ess (n?1) also accesses (n) but does not cause a match. 4.32.4.2.1.2 comparator b comparator b offers address, direction (r/w) and access size (wor d/byte) comparison. if the sze bit is set the access size (wor d or byte) is compared with the sz bit value such that only the spec ified size of access causes a match. thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match. assuming the access direction is not qualified (rwe=0), for simplicity, the size access considerations are shown in table 320 . table 319. comparator c access considerations condition for valid match comp c address rwe rw examples read and write accesses of addr[n] addr[n] (178) 0x ldaa addr[n] staa #$byte addr[n] write accesses of addr[n] addr[n] 1 0 staa #$byte addr[n] read accesses of addr[n] addr[n] 1 1 ldaa #$byte addr[n] note: 178. a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contai n the exact address from the code.
mm912_634 advance information, rev. 4.0 freescale semiconductor 216 access direction can also be used to qualify a match for compar ator b in the same way as described for comparator c in table 319 . 4.32.4.2.1.3 comparator a comparator a offers address, direction (r/w), access size (word/byte) and data bus comparison. table lists access considerations with data bus comparison. on word accesses the data byte of the lower address is mapped to dbgadh. access direction can also be used to qualify a match fo r comparator a in the same wa y as described for comparator c in table 319 . 4.32.4.2.1.4 comparator a data bus comparison ndb dependency comparator a features an ndb c ontrol bit, which allows data bus comparators to be configured to either trigger on equivalence or trigger on difference. this allows monitoring of a difference in the contents of an address location from an expected value. when matching on an equivalence (ndb=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (dbgadhm/dbgadlm) so that it is ignored in the comparis on. a match occurs when all data bus bits with corresponding mask bits set are equivalent. if all mask regi ster bits are clear, then a match is based on the address bus only, the data bus is ignored. when matching on a difference, mask bits can be cleared to ignore bit positions. a match occurs when any data bus bit with corresponding mask bit set is different. clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. in this case ad dress bus equivalence does not cause a match. table 320. comparator b access size considerations condition for valid match comp b address rwe sze sz8 examples word and byte accesses of addr[n] addr[n] (179) 00x movb #$byte addr[n] movw #$word addr[n] word accesses of addr[n] only addr[n] 0 1 0 movw #$word addr[n] ldd addr[n] note: 179. a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contai n the exact address from the code. table 321. comparator a matches when accessing addr[n] sze sz dbgadhm, dbgadlm access dh=dbgadh, dl=dbgadl comment 0 x $0000 byte word no data bus comparison 0x $ff00 byte, data(addr[n])=dh word, data(addr[n])=dh, data(addr[n+1])=x match data(addr[n]) 0 x $00ff word, data(addr[n])=x, data(addr[n+1])=dl match data(addr[n+1]) 0 x $00ff byte, data(addr[n])=x, data(addr[n+1])=dl possible unintended match 0 x $ffff word, data(addr[n])=dh, data(addr[n+1])=dl match data(addr[n], addr[n+1]) 0 x $ffff byte, data(addr[n])=dh, data(addr[n+1])=dl possible unintended match 1 0 $0000 word no data bus comparison 1 0 $00ff word, data(addr[n])=x, data(addr[n+1])=dl match only data at addr[n+1] 1 0 $ff00 word, data(addr[n])=dh, data(addr[n+1])=x match only data at addr[n] 1 0 $ffff word, data(addr[n])=dh, data(addr[n+1])=dl match data at addr[n] & addr[n+1] 1 1 $0000 byte no data bus comparison 1 1 $ff00 byte, data(addr[n])=dh match data at addr[n]
mm912_634 advance information, rev. 4.0 freescale semiconductor 217 4.32.4.2.2 range comparisons using the ab comparator pair for a range comp arison, the data bus can also be used for qualification by using the comparator a data registers. furthermore the dbgactl rw and rwe bits can be used to qualify the range comparison on either a read or a write access. the corresponding dbgbctl bits are ignored. t he sze and sz control bits are ignored in range mode. the comparator a tag bit is used to tag range comparisons. the co mparator b tag bit is ignored in range modes. in order for a range comparison us ing comparators a and b, both compea and compeb mu st be set; to disable range compar isons both must be cleared. the comparator a brk bit is used to for the ab range, the comparator b brk bit is ignored in range mode. when configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 4.32.4.2.2.1 inside range (compa_addr ? address ? compb_addr) in the inside range comparator mode, co mparator pair a and b can be configured fo r range comparisons. this configuration depends upon the control register (dbgc2). the match condition requires that a valid match for both comparators happens on the same bus cycle. a match condition on only one comparator is not valid. an aligned word access which straddles the range boundary is valid only if the al igned address is inside the range. 4.32.4.2.2.2 outside range (address < compa_addr or address > compb_addr) in the outside range comparator mode, comparator pair a and b can be configured for range comparisons. a single match condition on either of the comp arators is recognized as valid. an aligned word access which straddles the range boundary is val id only if the aligned address is outside the range. outside range mode in combination with tagging can be used to de tect if the opcode fetches are from an unexpected range. in forced match mode the outside range match would typically be activa ted at any interrupt vector fetch or register access. this c an be avoided by setting the upper range limit to $3fff f or lower range limit to $00000 respectively. 4.32.4.3 match modes (forced or tagged) match modes are used as qualifiers for a state sequencer change of state. the comparator control register tag bits select the match mode. the modes are described in the following sections. 4.32.4.3.1 forced match when configured for forced matching, a comparator channel matc h can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in dbgsr are set. the state control register fo r the current state determines the next state. forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent o f comparator rwe/rw settings. furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address. 4.32.4.3.2 tagged match if a cpu taghit occurs a transition to an other state sequencer state is initiated an d the corresponding dbgsr flags are set. fo r a comparator related taghit to occur, the db g must first attach tags to instructions as they are fetched fr om memory. when the tagged instruction reaches the execution stage of the instruction queue a taghit is generat ed by the cpu. this can initiate a s tate sequencer transition. 4.32.4.3.3 immediate trigger independent of comparator matches it is poss ible to initiate a tracing session and/or br eakpoint by writing to the trig bit in dbgc1. if configured for begin aligned tracing, this triggers the state sequencer into the final state, if configured for end alignment, setting the trig bit disarms the module, ending t he session and issues a forced breakpoint request to the cpu. table 322. ndb and mask bit dependency ndb dbgadhm[n] / dbgadlm[n] comment 0 0 do not compare data bus bit. 0 1 compare data bus bit. match on equivalence. 1 0 do not compare data bus bit. 1 1 compare data bus bit. match on difference.
mm912_634 advance information, rev. 4.0 freescale semiconductor 218 it is possible to set both trig and arm simultaneously to gener ate an immediate trigger, independe nt of the current state of arm. 4.32.4.3.4 chann el priorities in case of simultaneous matches the priority is resolved according to table 323 . the lower priority is suppressed. it is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. the priorities described in table 323 dictate that in the case of simultaneous matches, the match poi nting to final state has highest priority followed by the lower channel number (0,1,2). 4.32.4.4 state sequence control figure 67. state sequencer diagram the state sequencer allows a defin ed sequence of events to provide a trigger point for tracing of data in the trace buffer. onc e the dbg module has been armed by setting the arm bit in the db gc1 register, then state1 of t he state sequencer is entered. further transitions between the states are then controlled by the state control regist ers and channel matches. from final state the only permitted transition is back to the disarmed state0. transition between any of the states 1 to 3 is not restricted. ea ch transition updates the ssf[2:0] flags in dbgsr accordingly to indicate the current state. alternatively writing to the trig bit in dbgsc1, provides an immediate trig ger independent of comparator matches. independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the brk bits in the dbgxctl registers. thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be in itiated by a match on other channels. i f a debug session is ended by a match on a channel the state sequenc er transitions through final state for a clock cycle to state 0. this is independent of tracing and breakpoint activity, thus wi th tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. 4.32.4.4.1 final state on entering final state a trigger may be issued to the trace buff er according to the trace alignment control as defined by the talign bit (see section 4.32.3.2.3, ?debug trace control register (dbgtcr)? ). if the tsource bit in dbgtcr is clear then the trace buffer is disabled and the transition to final stat e can only generate a breakpoint request. in this case or upon completion of a tracing session when tracing is enabled, the ar m bit in the dbgc1 register is cleared, returning the module to table 323. channel priorities priority source action highest trig enter final state channel pointing to final state transition to next state as defined by state control registers match0 (force or tag hit) transition to next st ate as defined by state control registers match1 (force or tag hit) transition to next st ate as defined by state control registers lowest match2 (force or tag hit) transition to nex t state as defined by state control registers state1 final state state3 arm = 1 session complete (disarm) state2 state 0 (disarmed) arm = 0 arm = 0 arm = 0
mm912_634 advance information, rev. 4.0 freescale semiconductor 219 the disarmed state0. if tracing is enabled a breakpoint request ca n occur at the end of the trac ing session. if neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarme d. 4.32.4.5 trace buffer operation the trace buffer is a 64 lines deep by 20-bits wide ram array. t he dbg module stores trace information in the ram array in a circular buffer format. the system a ccesses the ram array through a register window (dbgtbh:dbgtbl) using 16-bit wide word accesses. after each complete 20-bit trace buffer line is read , an internal pointer into the ram increments so that the ne xt read receives fresh information. data is stored in the format shown in table 324 and table . after each store the counter register dbgcnt is incremented. tracing of cpu acti vity is disabled when the bdm is active. reading the trace buffer whilst the dbg is armed returns invalid data and the trace buffer pointer is not incremented. 4.32.4.5.1 trace trigger alignment using the talign bit (see section 4.32.3.2.3, ?debug tr ace control register (dbgtcr) ) it is possible to align the trigger with the end or the beginning of a tracing session. if end alignment is selected, tr acing begins when the arm bit in dbgc1 is set an d state1 is entered; t he transition to final st ate signals the end of the tracing session. tracing with begin-trigger starts at the opcode of the trigger. using end alignment or when the tracing is initiated by writing to the trig bit whilst c onfigured for begin alignment, tracing starts in the second cycle a fter the dbgc1 write cycle. 4.32.4.5.1.1 storing with begin trigger alignment storing with begin alignment, data is not stored in the trace buffer until the final st ate is entered. once the trigger conditi on is met the dbg module remains armed until 64 lines are stored in the trace buffer. if the trigge r is at the address of the change-of-flow instruction the c hange of flow associated with the trigger is st ored in the trace buffer. using begin alignment together with tagging, if the tagged instruction is about to be executed then the tr ace is started. upon completion of the trac ing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 4.32.4.5.1.2 storing with end trigger alignment storing with end alignment, data is stored in the trace buffer until the final state is entered , at which point the dbg module becomes disarmed and no more data is stored. if the trigger is at the address of a c hange of flow instruction, the trigger even t is not stored in the trace buffer. if all trace buffer lines have been used before a trigger event oc curs then the trace continues at the first line, overwriting the oldest entries. 4.32.4.5.2 trace modes four trace modes are available. the mode is selected using the trcmod bits in t he dbgtcr register. tracing is enabled using the tsource bit in the dbgtcr re gister. the modes are described in the following subsections. 4.32.4.5.2.1 normal mode in normal mode, change of flow (cof) program counter (pc) addresses are stored. cof addresses are defined as follows: ? source address of taken conditional branches (long, short, bit-conditional, and loop primitives) ? destination address of indexed jmp, jsr, and call instruction ? destination address of rti, rts, and rtc instructions ? vector address of interrupts, except for bdm vectors lbra, bra, bsr, bgnd as well as non-indexed jmp, jsr, and ca ll instructions are not classified as change of flow and are not stored in the trace buffer. stored information includes the full 18-bit address bus and info rmation bits, which contains a source/destination bit to indica te whether the stored address was a so urce address or destination address. note when a cof instruction with destination address is executed, the destination address is stored to the trace buffer on instruction comple tion, indicating the cof has taken place. if an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. the instruction at the destination address of the original program flow gets executed after the interrupt service routine.
mm912_634 advance information, rev. 4.0 freescale semiconductor 220 in the following example an irq interrupt occu rs during execution of the indexed jmp at address mark1. the brn at the destination (s ub_1) is not executed until after the irq service routine but the destination address is entered into the trace buffer to indicate that the indexed jmp cof has taken place. ldx #sub_1 mark1 jmp 0,x ; irq interrupt occurs during execution of this mark2 nop ; sub_1 brn * ; jmp destination address trace buffer entry 1 ; rti destination address trace buffer entry 3 nop ; addr1 dbne a,part5 ; source address trace buffer entry 4 irq_isr ldab #$f0 ; irq vector $fff2 = trace buffer entry 2 stab var_c1 rti ; the execution flow taking into account the irq is as follows ldx #sub_1 mark1 jmp 0,x ; irq_isr ldab #$f0 ; stab var_c1 rti ; sub_1 brn * nop ; addr1 dbne a,part5 ; 4.32.4.5.2.2 loop1 mode loop1 mode, similarly to normal mode also stores only cof addre ss information to the trace buffer , it however allows the filter ing out of redundant information. the intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the dbne instruction or po lling loops using brset/brclr instructions. immediately after address information is placed in the trace buffer, the dbg module writes this value into a background register. this prevents consecutive duplicate address entries in the tr ace buffer resulting from repeated branches. loop1 mode only inhibits consecutive duplic ate source address entries that would typically be stored in most tight looping constructs. it does not inhibit repeated entri es of destination addresses or vector a ddresses, since repeat ed entries of these would most likely indicate a bug in the user?s c ode that the dbg module is designed to help find. 4.32.4.5.2.3 detail mode in detail mode, address and data for all memory and register accesse s is stored in the trace buff er. this mode is intended to supply additional information on indexed, indirect addressi ng modes where storing only the destination address would not provide all information required for a user to determine where th e code is in error. this mode also features information bit st orage to the trace buffer, for each address byte storage. the informati on bits indicate the size of access (word or byte) and the typ e of access (read or write). when tracing in detail mode, all cycles are traced except those when the cpu is either in a free or opcode fetch cycle. 4.32.4.5.2.4 compressed pure pc mode in compressed pure pc mode, the pc addresses of all execut ed opcodes, including illegal opcodes are stored. a compressed storage format is used to increase the effective depth of the tr ace buffer. this is achieved by storing the lower order bits ea ch time and using 2 information bits to indicate if a 64 byte boun dary has been crossed, in which case the full pc is stored. each trace buffer row consists of 2 information bits and 18 pc address bits
mm912_634 advance information, rev. 4.0 freescale semiconductor 221 note: when tracing is terminated using forced br eakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoi nt can be stored to the trace buffer. the number of opcodes is dependent on program flow. this can be avoided by using tagged breakpoints. 4.32.4.5.3 trace buffer or ganization (normal, loop1, detail modes) adrh, adrm, adrl denote address high, middle and low byte respec tively. the numerical suffix refers to the tracing count. the information format for loop1 and normal modes is identical. in detail mode, the address and data for each entry are stored on consecutive lines, thus the ma ximum number of entries is 32. in this case dbgcnt bits are incremented twice, once for the address line and once for the data line, on each trace buffer entry . in detail mode cinf comp rises of r/w and size access information (crw and csz respectively). single byte data accesses in detail mode are always stored to the low byte of the trace buffer (datal) and the high byte is cleared. when tracing word accesses, the byte at the lower add ress is always stored to trace buffer byte1 and the byte at the higher address is stored to byte0. 4.32.4.5.3.1 informati on bit organization the format of the bits is dependent upon the active trace mode as described below. field2 bits in detail mode in detail mode the csz and crw bits indicate the type of access being made by the cpu. table 324. trace buffer organization (normal,loop1,detail modes) mode entry number 4-bits 8-bits 8-bits field 2 field 1 field 0 detail mode entry 1 cinf1,adrh1 adrm1 adrl1 0 datah1 datal1 entry 2 cinf2,adrh2 adrm2 adrl2 0 datah2 datal2 normal/loop1 modes entry 1 pch1 pcm1 pcl1 entry 2 pch2 pcm2 pcl2 table 325. field2 bits in detail mode bit 3 bit 2 bit 1 bit 0 csz crw addr[17] addr[16] table 326. field descriptions bit description 3 csz access type indicator ? this bit indicates if the access was a by te or word size when tracing in detail mode 0 word access 1 byte access 2 crw read write indicator ? this bit indicates if the corresponding stored address corresponds to a read or write access when tracing in detail mode. 0 write access 1 read access 1 addr[17] address bus bit 17 ? corresponds to system address bus bit 17. 0 addr[16] address bus bit 16 ? corresponds to system address bus bit 16.
mm912_634 advance information, rev. 4.0 freescale semiconductor 222 field2 bits in normal and loop1 modes 4.32.4.5.4 trace buffer organizati on (compressed pure pc mode) note configured for end aligned triggering in compressed purepc mode, then after rollover it is possible that the oldest base address is overwrit ten. in this case all entries between the pointer and the next base address have lost their base address following rollover. for example in ta b l e 3 2 9 if one line of rollover has occurred, line 1, pc1, is overwritten with a new entry. thus the entries on lines 2 and 3 have lost their base address. for reconstruction of program flow the first base address followi ng the pointer must be used, in the example, line 4. the pointer points to the oldest entry, line 2. figure 68. information bits pch bit 3 bit 2 bit 1 bit 0 csd cva pc17 pc16 table 327. pch field descriptions bit description 3 csd source destination indicator ? in normal and loop1 mode this bit indicate s if the corresponding stored address is a source or destination address. this bit has no meaning in compressed pure pc mode. 0 source address 1 destination address 2 cva vector indicator ? in normal and loop1 mode this bit indicates if the corresponding stored address is a vector address. vector addresses are destination addresses, thus if cva is se t, then the corresponding csd is also set. this bit has no meaning in compressed pure pc mode. 0 non-vector destination address 1 vector destination address 1 pc17 program counter bit 17 ? in normal and loop1 mode this bit corresponds to program counter bit 17. 0 pc16 program counter bit 16 ? in normal and loop1 mode this bit corresponds to program counter bit 16. table 328. trace buffer organization example (compressed purepc mode) mode line number 2-bits 6-bits 6-bits 6-bits field 3 field 2 field 1 field 0 compressed pure pc mode line 1 00 pc1 (initial 18-bit pc base address) line 2 11 pc4 pc3 pc2 line 3 01 0 0 pc5 line 4 00 pc6 (new 18-bit pc base address) line 5 10 0 pc8 pc7 line 6 00 pc9 (new 18-bit pc base address)
mm912_634 advance information, rev. 4.0 freescale semiconductor 223 field3 bits in compressed pure pc modes each time that pc[17:6] differs from the previous base pc[17:6], then a new base address is stored. the base address zero value is the lowest address in the 64 address range the first line of the trace buffer always gets a base pc address, this applies also on rollover. 4.32.4.5.5 reading da ta from trace buffer the data stored in the trace buffer can be read provided the dbg module is not armed, is configured for tracing (tsource bit is set) and the system not secured. when th e arm bit is written to 1 the trace buffer is locked to prevent reading. the trace b uffer can only be unlocked for reading by a single aligned word write to dbgtb when the module is disarmed. the trace buffer can only be read through the dbgtb register us ing aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. the trace buffer data is read out firs t-in first-out. by reading cnt in dbgcnt the number of valid lines c an be determined. dbgcnt does not decrement as data is read. whilst reading an internal pointer is used to determine the ne xt line to be read. after a tracing session, the pointer points t o the oldest data entry, thus if no rollover has occurred, the pointe r points to line0, otherwise it points to the line with the olde st entry. in compressed pure pc mode on rollover the line with the oldest data entry may also contain newer data entries in fields 0 and 1. thus if rollover is indicated by the tb f bit, the line status must be decoded usi ng the inf bits in field3 of that line. if both inf bits are clear then the line contains only entries from before the last rollover. if inf0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data. if inf1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data. the pointer is initialized by each aligned write to dbgtbh to point to the oldest data again. this enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. the least significant word of line is read out first. this corresponds to the fields 1 and 0 of ta b l e 3 2 4 . the next word read returns field 2 in the least significant bi ts [3:0] and ?0? for bits [15:4]. reading the trace buffer while the dbg module is armed return s invalid data and no shifting of the ram pointer occurs. 4.32.4.5.6 trace buff er reset state the trace buffer contents and dbgcnt bits are not initialized by a syst em reset. thus should a syst em reset occur, the trace session information from immediately before the reset occurred can be read out and the number of valid lines in the trace buffe r is indicated by dbgcnt. the internal pointer to the current trace buffer address is initialized by unlocking the trace buffer a nd points to the oldest valid data even if a reset occurred during the tracing session. to read the trace buffer after a reset, ts ource must be set, otherwise the trace buffer reads as all zeroes. gener ally debugging occurrences of system resets is best handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. the trace buffer contents and dbgcnt bits are undefined following a por. note an external pin reset that occu rs simultaneous to a trace buffe r entry can, in very seldom cases, lead to either that entry being co rrupted or the first entry of the session being corrupted. in such cases the other contents of the trace buffer still contain valid tracing information. the case occurs wh en the reset assertion coincides with the trace buffer entry clock edge. 4.32.4.6 tagging a tag follows program information as it advances through the instruction queue. when a tagged instruction reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition. table 329. compressed pure pc mode field 3 information bit encoding inf1 inf0 trace buffer row content 0 0 base pc address tb[17:0] contains a full pc[17:0] value 0 1 trace buffer[5:0] contain incremental pc relative to base address zero value 1 0 trace buffer[11:0] contain next 2 incremental pcs relative to base address zero value 1 1 trace buffer[17:0] contain next 3 incremental pcs relative to base address zero value
mm912_634 advance information, rev. 4.0 freescale semiconductor 224 each comparator control register features a tag bit, which co ntrols whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched add ress. if a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. using begin trigger together with tagging, if the tagged instru ction is about to be executed then the transition to the next st ate sequencer state occurs. if the transition is to the final state, tracing is started. only upon completion of the tracing sessio n can a breakpoint be generated. using end alignment, when the tagged instruction is about to be ex ecuted and the next transition is to final state then a breakpoint is generated immediat ely, before the tagged instruction is carried out. r/w monitoring, access size (sz) monitoring and data bus moni toring are not useful if tagging is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. thus these bits are ignored if tagging is selected. when configured for range comparisons and tagging, the ranges are accurate only to word boundaries. tagging is disabled when the bdm becomes active. 4.32.4.7 breakpoints it is possible to generate breakpoints from channel transitions to final state or using software to write to the trig bit in th e dbgc1 register. 4.32.4.7.1 breakpoi nts from comparator channels breakpoints can be generated when the state sequencer transiti ons to the final state. if configured for tagging, then the breakpoint is generated when the tagged opcode reac hes the execution stage of the instruction queue. if a tracing session is selected by the ts ource bit, breakpoints are requested when the tracing session has completed, thus if begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 330 ). if no tracing session is selected, break points are requested immediately. if the brk bit is set, then the associated breakpoint is g enerated immediately independent of tracing trigger alignment. 4.32.4.7.2 breakpoints gene rated via the trig bit if a trig triggers occur, the final state is entered whereby trac ing trigger alignment is defined by the talign bit. if a traci ng session is selected by the tsource bit, breakpoints are reque sted when the tracing session has completed, thus if begin aligned triggering is selected, the breakpoint is requ ested only on completion of the subsequent trace (see ta b l e 3 3 0 ). if no tracing session is selected, breakpoints are requested immediat ely. trig breakpoints are possib le with a single write to dbgc1, setting arm and trig simultaneously. 4.32.4.7.3 breakpoi nt priorities if a trig trigger occurs after begin aligned tracing has alre ady started, then the trig no longer has an effect. when the associated tracing session is complete, the breakpoint occurs. similarly if a trig is follow ed by a subsequent comparator channel match, it has no effect, si nce tracing has already started. if a forced swi breakpoint coincides with a bgnd in user code with bdm enabled, then the bdm is activated by the bgnd and the breakpoint to swi is suppressed. 4.32.4.7.3.1 dbg breakpoint priorities and bdm interfacing breakpoint operation is dependent on the state of the bdm module . if the bdm module is active , the cpu is executing out of bdm firmware, thus comparator matches and associated breakpoin ts are disabled. in addition, while executing a bdm trace command, tagging into bdm is disabled. if bdm is not active, th e breakpoint gives priority to bdm requests over swi requests table 330. breakpoint setup for cpu breakpoints brk talign dbgbrk breakpoint alignment 0 0 0 fill trace buffer until tri gger then disarm (no breakpoints) 0 0 1 fill trace buffer until trigger, then breakpoint request occurs 0 1 0 start trace buffer at trigger (no breakpoints) 0 1 1 start trace buffer at trigger. a breakpoi nt request occurs when trace buffer is full 1 x 1 terminate tracing and generate br eakpoint immediately on trigger 1 x 0 terminate tracing immediately on trigger
mm912_634 advance information, rev. 4.0 freescale semiconductor 225 if the breakpoint happens to coincide with a swi instruction in us er code. on returning from bdm, the swi from user code gets executed. bdm cannot be entered from a breakpoint unless the enable bit is set in the bdm. if entry to bdm via a bgnd instruction is attempted and the enable bit in the bdm is cleared, the cpu ac tually executes the bdm firmwa re code, checks the enable and returns if enable is not set. if not serviced by the monito r then the breakpoint is re-asse rted when the bdm returns to nor mal cpu flow. if the comparator register c ontents coincide with the swi/bdm vector address then an swi in user code could coincide with a dbg breakpoint. the cpu ensures that bdm requests have a highe r priority than swi requests. returning from the bdm/swi service routine care must be taken to avoid a repeated breakpoint at the same address. should a tagged or forced breakpoint coincide with a bgnd in user code, then the instruction that follows the bgnd instruction is the first instruction executed when normal program execution resumes. note when program control returns from a tagged br eakpoint using an rti or bdm go command without program counter modification it return s to the instruction whose tag generated the breakpoint. to avoid a repeated breakpoint at the same location reconfigure the dbg module in the swi routine, if configured for an swi breakpoint, or over the bdm interface by executing a trace command before the go to increment the program flow past the tagged instruction. 4.32.5 application information 4.32.5.1 state machine scenarios defining the state control registers as scr1,scr2, scr3 and m0,m1,m2 as matches on channels 0,1,2 respectively. scr encoding supported by s12sdbgv1 are show n in black. scr encoding supported only in s12sdbgv2 are shown in red. for backwards compatibility the new scenarios use a 4th bit in each scr register. thus the existing encoding for scrx[2:0] is not changed. 4.32.5.2 scenario 1 a trigger is generated if a given s equence of 3 code events is executed. figure 69. scenario 1 scenario 1 is possible with s12sdbgv1 scr encoding 4.32.5.3 scenario 2 a trigger is generated if a given s equence of 2 code events is executed. table 331. breakpoint mapping summary dbgbrk bdm bit (dbgc1[4]) bdm enabled bdm active breakpoint mapping 0 x x x no breakpoint 1 0 x 0 breakpoint to swi x x 1 1 no breakpoint 1 1 0 x breakpoint to swi 1 1 1 0 breakpoint to bdm state1 final state state3 state2 scr1=0011 scr2=0010 scr3=0111 m1 m2 m0
mm912_634 advance information, rev. 4.0 freescale semiconductor 226 figure 70. scenario 2a a trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (compa,compb configured for range mode). m1 is disabled in range modes. figure 71. scenario 2b a trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range (compa,compb configured for range mode) figure 72. scenario 2c all 3 scenarios 2a,2b,2c are possibl e with the s12sdbgv1 scr encoding 4.32.5.4 scenario 3 a trigger is generated immediately when one of up to 3 given events occurs figure 73. scenario 3 scenario 3 is possible with s12sdbgv1 scr encoding 4.32.5.5 scenario 4 trigger if a sequence of 2 events is carried out in an incorrect order. event a must be followed by event b and event b must be followed by event a. 2 consecutive occurr ences of event a without an intermediate event b cause a trigger. similarly 2 consecutive occurrences of event b without an intermediate event a cause a trigger. this is possible by using compa and compc to match on the same address as shown. figure 74. scenario 4a state1 final state state2 scr1=0011 scr2=0101 m1 m2 state1 final state state2 scr1=0111 scr2=0101 m01 m2 state1 final state state2 scr1=0010 scr2=0011 m2 m0 state1 final state scr1=0000 m012 state1 state 3 final state state2 m0 m0 m2 m1 m1 m1 scr1=0100 scr2=0011 scr3=0001
mm912_634 advance information, rev. 4.0 freescale semiconductor 227 this scenario is currently not possible us ing 2 comparators only. s12sdbgv2 makes it possible with 2 comparators, state 3 allowing a m0 to return to state 2, whilst a m2 leads to final state as shown. figure 75. scenario 4b (with 2 comparators) the advantage of using only 2 channels is that now range comparisons can be included (channel0) this however violates the s12sdbgv1 specif ication, which states that a match leading to final state always has priority in case of a simultaneous match, whilst priority is also given to t he lowest channel number. for s12sdbg the corresponding cpu priority decoder is removed to support this, such t hat on simultaneous taghits, taghits pointing to final state have highest priority. i f no taghit points to final state then the lowest channel number has pr iority. thus with the above encoding from state3, the cpu and dbg would break on a simultaneous m0/m2. 4.32.5.6 scenario 5 trigger if following event a, event c precedes event b. i.e. the expected execution flow is a->b->c. figure 76. scenario 5 scenario 5 is possible with the s12sdbgv1 scr encoding 4.32.5.7 scenario 6 trigger if event a occurs twice in succession before any of 2 ot her events (bc) occurs. this scenario is not possible using the s12sdbgv1 scr encoding. s12sdbgv2 incl udes additions shown in red. the change in scr1 encoding also has the advantage that a state1->state3 transition using m0 is now possible. this is advantageous because range and data bus comparisons use channel0 only. figure 77. scenario 6 4.32.5.8 scenario 7 trigger when a series of 3 events is exec uted out of order. specifying the event order as m1,m2,m0 to run in loops (120120120). any deviation from that order should tr igger. this scenario is not possible usi ng the s12sdbgv1 scr encoding because or possibilities are very limited in the channel encoding. by addi ng or forks as shown in red this scenario is possible. state1 state 3 final state state2 m0 m01 m0 m2 m2 m2 scr1=0110 scr2= 1100 scr3= 1110 m1 disabled in range mode state1 final state state2 scr1=0011 scr2=0110 m1 m0 m2 state1 final state state3 scr1= 1001 scr3= 1010 m0 m0 m12
mm912_634 advance information, rev. 4.0 freescale semiconductor 228 figure 78. scenario 7 on simultaneous matches the lowest channel number has priority so with this configuration th e forking from state1 has the peculiar effect that a simultaneous match0 /match1 transitions to final state but a simultaneous match2/match1transitions to state2. 4.32.5.9 scenario 8 trigger when a routine/event at m2 follows either m1 or m0. figure 79. scenario 8a trigger when an event m2 is followed by either event m0 or event m1 figure 80. scenario 8b scenario 8a and 8b are possible with the s12sdbgv1 and s12sdbgv2 scr encoding. 4.32.5.10 scenario 9 trigger when a routine/event at a (m2) does not follow either b or c (m1 or m0) before they are executed again. this cannot be realized with thes12sdbgv1 scr encoding due to or limitatio ns. by changing the scr2 encoding as shown in red this scenario becomes possible. figure 81. scenario 9 4.32.5.11 scenario 10 trigger if an event m0 occurs following up to two successive m2 events without the resetting event m1. as shown up to 2 consecutive m2 events are allowed, whereby a reset to state1 is possible after either one or two m2 events. if an event m0 occu rs following the second m2, before m1 resets to state1 then a trigge r is generated. configuring compa and compc the same, it is possible to generate a breakpoint on the third co nsecutive occurrence of event m0 without a reset m1. state1 final state state3 state2 scr1= 1101 scr2= 1100 scr3= 1101 m1 m2 m12 m0 m02 m01 state1 final state state2 scr1=0111 scr2=0101 m01 m2 state1 final state state2 scr1=0010 scr2=0111 m2 m01 state1 final state state2 scr1=0111 scr2= 1111 m01 m01 m2
mm912_634 advance information, rev. 4.0 freescale semiconductor 229 figure 82. scenario 10a figure 83. scenario 10b scenario 10b shows the case that after m2 then m1 must occur bef ore m0. starting from a particul ar point in code, event m2 must always be followed by m1 before m0. if after any m2, ev ent m0 occurs before m1 then a trigger is generated. state1 final state state3 state2 scr1=0010 scr2=0100 scr3=0010 m2 m2 m0 m1 m1 state1 final state state3 state2 scr1=0010 scr2=0011 scr3=0000 m2 m1 m0 m0
mm912_634 advance information, rev. 4.0 freescale semiconductor 230 4.33 security (s12x9secv2) 4.33.1 introduction this specification describes the fu nction of the security mechanism in the s12i chip family (9sec). note no security feature is absolutely secure. however, freescale?s strategy is to make reading or copying the flash and/or eeprom difficult for unauthorized users. 4.33.1.1 features the user must be reminded that pa rt of the security must lie with the applicati on code. an extreme example would be application code that dumps the contents of the internal memory. this woul d defeat the purpose of security. at the same time, the user may also wish to put a backdoor in the application program. an exampl e of this is the user downloads a security key through the sci , which allows access to a programming routine that updates parameters stored in another section of the flash memory. the security features of the s12i chip family (in secure mode) are: ? protect the content of non-volatile memo ries (flash, eeprom) ? execution of nvm commands is restricted ? disable access to internal memory via background debug module (bdm) 4.33.1.2 modes of operation table 332 gives an overview over availability of security relevant features in unsecure and secure modes. figure 84 shows all modules affected by security in an mcu. table 332. feature availability in unsecure and secure modes on s12i unsecure mode secure mode ns ss nx es ex st ns ss nx es ex st note: 180. restricted nvm command set only. please refer to th e nvm wrapper block guides for detailed information. 181. bdm hardware commands restricted to peripheral registers only.
mm912_634 advance information, rev. 4.0 freescale semiconductor 231 figure 84. chip security block diagram the security mechanism relies on non-volatile bits contained in the flash module. the state of these bits is passed to the s12xmmc. several of the mcu modules are involved in blocking ce rtain operations which would reveal the contents of the protected flash and eeprom. 4.34 impact on mcu modules when the device is in secure mode, the following blocks are af fected by security 4.34.1 mmc there is a signal called ?secreq? from the flash or eeprom which indicates if the security is enabled. there is also a signal from the xbdm, which is used in the proce ss of unsecuring the chip. this signal is called ?unsecure?. these two signals and the resulting state of ?device security? are shown in table 333 . in expanded modes, if the ?mmc_secure_t2? signal is asserted, the romon and eeon bits are forced to zero. this operation is independent of how the part got to expanded mode (str aight out of reset or by writing the mode register). when security is enabled and the part is brought up in specia l single chip mode, the secure bdm firmware is brought into the map along with the standard bdm firmware. the secure firmware has higher priority, but does not fill the whole space. it occupi es $7f_ff80 to $7f_ffff. table 333. : security bits - system control secreq bdm_unsecure mmc_secure 0 0 0 (unsecured) 0 1 0 (unsecured) 1 0 1 (secured) 1 1 0 (unsecured) eeprom xgate xdbg security control security status secreq xmmc flash xbdm mmc_secure unsecure
mm912_634 advance information, rev. 4.0 freescale semiconductor 232 one cycle after bdm_unsecure is asserted the secure firmware is disabled from the map. in secure mode abdm access to a non register address will be tr anslated to a peripheral register address, and bdm registers are not accessible. no bdm global access is possibl e if the chip is secured. in secured expanded mode or emulation mode , flash and eeprom are disabled by the mmc. 4.34.2 bdm when security is active and the blank check is performed an d failed, only bdm hardware commands are available. if the blank check is succeeds, all bdm commands are available. the bdm status register contains a bit called unsec. this bit is only writable by the secure firmware in special single chip mo de. based on the state of this bit, the bdm generates a signal ca lled ?unsecure?. the bit and signal are always reset to 0 (= de-asserted = secure). if the user resets into special single chip mode with the part secured, an alternate bdm firmware (?secure firmware?), is place d in the map along with the standard bdm firmware. the secure firmw are has higher priority than t he standard firmware, but it is smaller (less bytes). the secure firmware co vers the vector space, but does not reac h the beginning of the bdm firmware space. when blank check is successfully performe d, unsec is asserted. the bdm program jumps to the start of the standard bdm firmware program and the secure firmware is turned off. if the bl ank check fails, then the enbdm bit in the bdmsts register is set without asserting unsec, and the bdm firmware code enters a loop. this enables the bdm hardware commands. in secure mode the mmc restricts bdm accesses to the register space. with unsec asserted, security is off and the user can change the state of the secure bits in the flash. note that if the user does not change the state of these bits to ?unsecured?, the pa rt will be secured again when it is next taken out of reset. 4.34.3 dbg s12x_dbg will disable the trace buffer, but breakpoints are still valid. 4.34.4 xgate xgate internal registers xgccr, xgpc, and xgr1 - xg r7 can not be written and will read zero from ipbi. single stepping in xgate is not possible. xgate code residing in the internal ram cannot be protected: 1. start mcu in nsc, let it run for a while 2. reset into ssc, masers the nvm 3. reset into ssc, bl ank check of bdm secu re firmware succeeds 4. mcu is temporarily unsecured 5. bdm can be used to read internal ram (contents not affected by reset) 4.35 secure firmware code overview the bdm contains a secure firmware code. this firmware code is in voked when the user comes out of reset in special single chip mode with security enabled. the function of the firmware code is straight forward: ? verify the flash is erased ? verify the eeprom is erased ? if both are erased, release security if either the flash or the eepr om is not erased, then security is not releas ed. the enbdm bit is set and the code enters a loop. this allows bdm hardware commands, which may be used to erase the eeprom and flash. note that erasing the memories and erasing / reprogramming the se curity bits is not part of the firmware code. the user must perform these operations. the blank check of flash and eeprom is done in the bdm firmware. as such it could be changed on future parts. the current scheme uses the nvm command state-machines (ftx, eetx) to perform the blank check.
mm912_634 advance information, rev. 4.0 freescale semiconductor 233 4.35.0.1 securing the microcontroller once the user has programmed the flash and eeprom, the chip can be secured by progr amming the security bits located in the options/security byte in the flash me mory array. these non-volatile bits will keep the device secured through reset and power-down. the options/security byte is located at address 0xff0f (= global address 0x7f_ff0f) in the flash memory array. this byte can be erased and programmed like any other flash location. two bits of this byte are used for security (sec[1 :0]). on devices whic h have a memory page window, the flash options/security byte is also available at address 0xbf0f by selecting page 0x3f with the ppage register. the contents of this byte are copied into the flash security register (fsec) during a reset sequence. the meaning of the bits keyen[1:0] is shown in table 335 . please refer to section 4.35.0.3.2, ?unsec uring the mcu using the backdoor key access? for more information. the meaning of the security bits sec[1:0] is shown in table 336 . for security reasons, the state of device security is controlled by two bits. to put the device in unsecured mode, these bits must be programmed to sec[1:0] = ?10?. all other combinations put the device in a secured mode. the recommended value to put the de vice in secured state is the in verse of the unsecured state, i.e. sec[1:0] = ?01?. note please refer to the flash block guide for actual security configuration (in section ?flash module security?). 4.35.0.2 operation of the secured microcontroller by securing the device, unauthorized acce ss to the eeprom and flash memory content s can be prevented. however, it must be understood that the security of the e eprom and flash memory contents also depends on the design of the application program. for example, if the app lication has the capability of downloading code th rough a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the eeprom and flash memory contents even when the microcontro ller is in the secure state. in this ex ample, the security of the application co uld be enhanced by requiring a challenge/response auth entication before any code can be downloaded. secured operation has the following effects on the microcontroller: 4.35.0.2.1 normal single chip mode (ns) ? background debug module (bdm) operation is completely disabled. ? execution of flash and eeprom comm ands is restricted. plea se refer to the nvm block guide for details. ? tracing code execution using the dbg module is disabled. table 334. flash options/security byte 76543210 0xff0f keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 table 335. backdoor key access enable bits keyen[1:0] backdoor key access enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) table 336. security bits sec[1:0] security state 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured)
mm912_634 advance information, rev. 4.0 freescale semiconductor 234 4.35.0.2.2 speci al single chip mode (ss) ? bdm firmware commands are disabled. ? bdm hardware commands are restricted to the register space. ? execution of flash and eeprom comm ands is restricted. plea se refer to the nvm block guide for details. ? tracing code execution using the dbg module is disabled. special single chip mode means bdm is active after reset. th e availability of bdm firmware commands depends on the security state of the device. the bdm secure firmware first performs a blank check of both the flash memory and the eeprom. if the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate flash memor y location can be changed if the blank check fails, security will remain active, only the bdm hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. this will allow the bdm to be used to erase the eeprom and flash memory without giving access to their contents. after eras ing both flash memory and eeprom, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to ?unsecured? state via bdm. while the bdm is executing the blank check, the bdm interface is completely blocked, which means t hat all bdm commands are temporarily blocked. 4.35.0.2.3 executing from intern al memory in expanded mode the user may choose to operate from internal memory while in expanded mode. to do this the user must start in single chip mode and write to the mode bits selecting expanded operation. in this mode internal visibility and ipipe are blocked. if the users program tries to execute from outside t he program memory space (internal space occupied by the flash), the flash and eeprom will be disabled. bdm operations will be blocked. 4.35.0.3 if the user begins operat ion in single chip mode with security on, the user is constrained to operate out of internal memory - even if the user changes to expanded mode. to accomplish this the mmc needs to register that the part started in single chip mode and was secured. the cpu will provide the state of the two high-order bits of the program counter. all this information, plus the firmwar e size information is used to determine that the part is executing in the proper space. if the program strays, the selects for flash and eeprom are disabled by the mmc until the part goes through reset. 4.35.0.3.1 unsecuring the microcontroller unsecuring the microcontroller can be done by three different methods: 1. backdoor key access 2. reprogramming the security bits 3. complete memory erase (special modes) 4.35.0.3.2 unsecuring the mcu using the backdoor key access in normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. this method requires that: ? the backdoor key at 0xff00?0xff07 (= global addresse s 0x7f_ff00?0x7f_ff07) has been programmed to a valid value. ? the keyen[1:0] bits within the flash options/security byte select ?enabled?. ? in single chip mode, the application program programmed in to the microcontroller must be designed to have the capability to write to the backdoor key locations. the backdoor key values themselves would not normally be st ored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). the backdoor key access method allows debugging of a secured mi crocontroller without having to erase the flash. this is particularly useful for failure analysis. note no word of the backdoor key is allowed to have the value 0x0000 or 0xffff. 4.35.0.4 reprogramming the security bits in normal single chip mode (ns), security can also be disabled by erasing and reprogramming the security bits within flash options/security byte to the unsecured va lue. because the erase oper ation will erase the entire sector from 0xfe00?0xffff (0x7f_fe00?0x7f_ffff), the backdoor key and the interrupt vect ors will also be erased; this method is not recommended for
mm912_634 advance information, rev. 4.0 freescale semiconductor 235 normal single chip mode. the application software can only erase and program the flash options/security byte if the flash secto r containing the flash options/securit y byte is not protected (see fl ash protection). thus flash protection is a useful means of preventing this method. the microcontroller will enter the unsecu red state after the next reset following the programming of th e security bits to the unsecured value. this method requires that: ? the application software previously programmed into the mi crocontroller has been designed to have the capability to erase and program the flash optio ns/security byte, or security is first disa bled using the backdoor key method, allowing bdm to be used to issue commands to erase and program the flash options/security byte. ? the flash sector containing the flash options/security byte is not protected. 4.35.0.5 complete memory erase (special modes) the microcontroller can be unsecured in special modes by erasing the entire eeprom and flash memory contents. when a secure microcontroller is reset into special single chip mode (ss), the bdm firmware verifies whether the eeprom and flash memory are erased. if any eeprom or flash memory addr ess is not erased, only bdm hardware commands are enabled. bdm hardware commands can then be used to write to the eeprom and flash regist ers to mass erase th e eeprom and all flash memory blocks. when next reset into special single chip mode, the bdm firmw are will again verify whether all eeprom and flash memory are erased, and this being the case, will enable all bdm commands, allowing the flash options/securit y byte to be programmed to the unsecured value. the security bits sec[1:0] in the flash secu rity register will indicate the unsecure state following the n ext reset. 4.36 initialization of a virgin device ?virgin? cells in the flash array will read all programmed and th e mcu will be secured as the sec[1:0] bits would be loaded wit h ?00? from the flash security byte. at wafer probe nvm bist mode is used to test and initialize the flash ifr block. wafer probe will leave the flash block erased so the mcu will be secured. for blind-assembled products, the following sequenc e must be used to initialize the flash array: ? reset the mcu into special mode. ? set fclkdiv to provide a proper fclk period. ? set fprot register to the unprotected state. ? set the wrall bit in the ft stmod register, if available. ? load the flash pulse timer with the mass erase ti me by executing a ldptmr command write sequence. ? execute masersi commands to mass erase the flash main block and flash ifr block. ? execute the ldptmr and pgmi command write sequence to program all timing parameters into the flash ifr block. ? reset the mcu into special single chip mode. after th e reset the bdm secure firmware executes a blank check command. if the blank check succeeds the mcu will be temporarily unsecured. ? execute the pgm command write sequence to prog ram the security byte to the unsecured state. blocking access to memories which can be secured during scan testing is necessary. while it would take a fair amount of sophistication on the part of a ?thief?, our dft people still cons ider this a major risk to security. it is therefore highly re commended that accesses to the flash and eeprom arra ys be blocked at chip level during scan test. blocking or not blocking security at the core level will not help this. 4.37 impact of security on test when silicon comes out of processing, it is extremely unlikely that the security bits will be configured for unsecure. there wi ll need to be ?hooks? for running bist (if present) or burn-in by bypassing the security. if wafer level burn-in is to be used, security must have a bypa ss which can be connected to by the burn-in layer. in burn-in, security is bypassed, but when the burn-in layer is removed, th e state of secreq determines whether the part is secured or not. this may require some sort of weak pul l-up device. at some point during testing the internal flash and eeprom will need to be unsecured. this test program should follow the same sequence as a user to unsecure the part: erase the memories, bring the part up in special mode, erase and program the security bits to the unsecured state.
mm912_634 advance information, rev. 4.0 freescale semiconductor 236 4.38 s12 clock, reset and power management unit (s12cpmu) 4.38.1 introduction this specification describes the function of the clock, re set and power management unit. ? the pierce oscillator (osclcp) provides a robust, low-no ise and low-power external clock source. it is designed for optimal start-up margin with typical crystal oscillators. ? the voltage regulator (ivreg) operates from the range 3.13 to 5.5 v. it provides all the requ ired chip internal voltages and voltage monitors. ? the phase locked loop (pll) provides a highly accurate frequency multiplier with internal filter. ? the internal reference clock (irc1m) provides a 1.0 mhz clock. 4.38.1.1 features the pierce oscillator (osclcp) contains ci rcuitry to dynamically contro l current gain in the output amplitude. this ensures a signal with low harmonic distortion, low power and good noise immunity. ? supports crystals or resonators from 4.0 to 16 mhz. ? high noise immunity due to input hysteresis and spike filtering. ? low rf emissions with peak-to- peak swing limited dynamically ? transconductance (gm) sized for optimum start-up margin for typical crystals ? dynamic gain control eliminates the nee d for external current limiting resistor ? integrated resistor eliminates the need for external bias resistor. ? low power consumption: operates from internal 1.8 v (nominal ) supply, amplitude control limits power the voltage regulator (ivreg) has the following features: ? input voltage range from 3.13 to 5.5 v ? low-voltage detect (lvd) with low-voltage interrupt (lvi) ? power-on reset (por) ? low-voltage reset (lvr) ? during scan pattern execution option to go to rpm to support iddq test. ? external voltage reference used for hv-stress test and mim screen, the external voltage on vdda, divided by series resistors, will be used as input to the regulating loop of the ivreg the phase locked loop (pll) has the following features: ? highly accurate and phase locked frequency multiplier ? configurable internal filter for best stability and lock time. ? frequency modulation for defined jitter and reduced emission ? automatic frequency lock detector ? interrupt request on entry or exit from locked condition ? reference clock either external (crystal) or internal square wave (1.0 mhz irc1m) based. ? pll stability is sufficient for lin communica tion, even if using irc1 m as reference clock the internal reference clock (irc1m) has the following features: ? trimmable in frequency ? factory trimmed value for 1.0 mhz in flash memory , can be overwritten by application if required other features of the s12cpmu include ? clock monitor to detect loss of crystal ? autonomous periodical interrupt (api) ? bus clock generator ? clock switch to select either pllclk or external crystal/resonator based bus clock ? pllclk divider to adjust system speed ? system reset generation from the following possible sources: ? power-on reset (por) ? low-voltage reset (lvr) ? illegal address access ? cop timeout ? loss of oscillation (clock monitor fail) ? external pin reset
mm912_634 advance information, rev. 4.0 freescale semiconductor 237 4.38.1.2 modes of operation this subsection lists and briefly describes al l operating modes supported by the s12cpmu. 4.38.1.2.1 run mode the voltage regulator is in full performance mode (fpm). the phase-locked loop (pll) is on. the internal reference clock (irc1m) is on. the api is available. ? pll engaged internal (pei) ? this is the default mode after system reset and power-on reset. ? the bus clock is based on the pllclk. ? after reset the pll is configured for 64 mhz vcoclk operation post divider is 0x03, so pllclk is vcoclk divid ed by 4, that is 16 mhz and bus clock is 8.0 mhz. the pll can be reconfigured for other bus frequencies. ? the reference clock for the pll (refclk) is based on internal reference clock irc1m ? pll engaged external (pee) ? the bus clock is based on the pllclk. ? this mode can be entered from default mo de pei by performing the following steps: ? configure the pll for desired bus frequency. ? program the reference divider (ref div[3:0] bits) to divide down oscillator frequency if necessary. ? enable the external oscillator (osce bit) ? pll bypassed external (pbe) ? the bus clock is based on the oscillator clock (oscclk). ? this mode can be entered from default mo de pei by performing the following steps: ? enable the external oscillator (osce bit) ? wait for oscillator to start up (uposc=1) ? select the oscillator clock (oscclk) as bus clock (pllsel=0) ? the pllclk is still on to filter possible spikes of the external oscillator clock 4.38.1.2.2 stop mode this mode is entered by executing the cpu stop instruction. the voltage regulator is in reduced power mode (rpm) the api is available the phase locked loop (pll) is off the internal reference clock (irc1m) is off core clock, bus clock and bdm clock are stopped depending on the setting of the pstp and the osce bit, stop mode can be differentiated between full stop mode (pstp = 0 or osce=0) and pseudo stop mode (pstp = 1 and osce=1). ? full stop mode (pstp = 0 or osce=0) the external oscillator (osclcp) is disabled after wake-up from full stop mode the core clock and bus clock are running on pllclk (pllsel=1). after wake-up from full stop mode the cop and rti are running on ircclk (coposcsel=0, rtioscsel=0) ? pseudo stop mode (pstp = 1 and osce=1) the external oscillator (osclc p) continues to run. if the respective enabl e bits are set the cop and rti will continue to run. the clock configuration bits pllsel, coposcsel, rtioscsel are unchanged note when starting up the external oscillator (either by programming osce bit to 1 or on exit from full stop mode with osce bit already 1) th e software must wait for a minimum time equivalent to the startup-time of the external oscillator t uposc before entering pseudo stop mode.
mm912_634 advance information, rev. 4.0 freescale semiconductor 238 4.38.1.3 s12cpmu block diagram figure 85. block diagram of s12cpmu s12cpmu extal xtal system reset power-on detect pll lock interrupt mmc illegal address access cop time out loop reference divider cop watchdog voltage vddr internal reset generator divide by phase post divider 1,2,?,32 vcoclk eclk2x lockie irctrim[9:0] syndiv[5:0] lock refdiv[3:0] 2*(syndiv+1) pierce oscillator 4mhz-16mhz osce ilaf porf divide by 2 eclk postdiv[4:0] power-on reset controlled locked loop with internal filter (pll) refclk fbclk reffrq[1:0] vcofrq[1:0] lock detect regulator 3.13 to 5.5v autonomous periodic interrupt (api) api interrupt vdda vssa adaptive oscillator filter pllsel oscfilt[4:0] (to mscan) vddx vssx vss low voltage detect vddx lvrf pllclk reference divide by 8 bdm clock clock (irc1m) clock monitor monitor fail real time interrupt (rti) rti interrupt pstp cpmurti oscillator status interrupt (osclcp) can_oscclk low voltage interrupt aclk apiclk rticlk ircclk oscclk rtioscsel cpmucop copclk ircclk oscclk coposcsel to reset generator cop time out pce pre uposc=0 sets pllsel bit api_extclk rc osc. vdd, vddf (core supplies) uposc reset oscie apie rtie lvds lvie low voltage detect vdda uposc uposc=0 clears & oscclk divide by 4 bus clock ircclk (to lcd) oscbw (bus clock) (core clock)
mm912_634 advance information, rev. 4.0 freescale semiconductor 239 figure 86 shows a block diagram of the osclcp. figure 86. osclcp block diagram 4.38.2 signal description this section lists and describes the signals that connect off chip. 4.38.2.1 reset r eset is an active-low bidirectional pin. as an input it initializ es the mcu asynchronously to a known start-up state. as an open-drain output it indicates that an mcu-internal reset has been triggered. 4.38.2.2 extal and xtal these pins provide the interface for a crystal to control the inte rnal clock generator circuitry. extal is the external clock i nput or the input to the crystal oscillator amplifier. xtal is the out put of the crystal oscillator amplifier. the mcu internal oscclk is derived from the extal input frequency. if osce=0, the extal pin is pulled down by an internal resistor of approximately 200 k ? and the xtal pin is pulled down by an internal resistor of approximately 700 k ? . note freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. lo op controlled circuit is not suited for overtone resonators and crystals. 4.38.2.3 vddr ? regulator power input pin pin v ddr is the power input of ivreg. all currents sourced into the regulator loads flow through this pin. an off-chip decoupling capacitor (100 nf...220 nf, x7r ceramic) between v ddr and v ss can smooth ripple on v ddr . extal xtal gain control vdd = 1.8 v rf oscclk peak detector vss
mm912_634 advance information, rev. 4.0 freescale semiconductor 240 4.38.2.4 vss ? ground pin 4.38.2.5 vss must be grounded. vdda, vssa ? regulator reference supply pins pins v dda and v ssa are used to supply the analog parts of the regulator. internal precision reference circuits are supplied from these signals. an off-chip decoupling capacitor (100 nf...220 nf, x7r ceramic) between v dda and v ssa can improve the quality of this supply. 4.38.2.6 vddx, vssx? pad supply pins this supply domain is monitored by the low voltage reset circuit. an off-chip decoupling capacitor (100 nf...220 nf, x7r cerami c) between vddx and vssx can improve the quality of this supply. note depending on the device package following device supply pins are maybe combined into one supply pin: vddr, vddx and vdda. depending on the device package following device supply pins are maybe combined into one supply pin: vss, vssx and vssa. please refer to the device reference manual for information if device supply pins are combined into one supply pin for certain packages and which supply pins are combined together. an off-chip decoupling capacitor (100 nf...220 nf, x7r ceramic) between the combined supply pin pair can improve the quality of this supply. 4.38.2.7 vdd ? internal regulator output supply (core logic) node vdd is a device internal supply output of the voltage regu lator that provides the power supply for the core logic. this su pply domain is monitored by the low voltage reset circuit. 4.38.2.8 vddf ? internal regulator output supply (nvm logic) node vddf is a device internal supply out put of the voltage regulator that provides the power supp ly for the nvm logic. this supply domain is monitored by the low voltage reset circuit 4.38.2.9 api_extclk ? api external clock output pin this pin provides the signal selected via apies and is enabled wit h apiea bit. see device specificat ion to which pin it connect s. 4.38.2.10 vddf_test, vdd_test, vddpll_test ? supply testmode pins these pins allow to measure internal vddf, vdd, vddpll. 4.38.2.11 cpmu_test_clk this signal is connected to a device pin and allows m easuring internal clocks if cpmu_test_clk_en bit is set. 4.38.2.12 cpmu_test_xfc this signal is connected to a device pin and allows measuring the internal pll filter node if cpmu_test_xfc_en bit is set. 4.38.2.13 regft[2:0] and regt[2:0] with the ipt_trim_ld_en signal of the pti, the trim values for vdd and vddf of th e vreg are loaded into cpmutest3 register which directly trims the vreg. 4.38.3 memory map and registers this section provides a detailed description of all registers accessible in the s12cpmu. 4.38.3.1 module memory map the s12cpmu registers are shown in figure 337 .
mm912_634 advance information, rev. 4.0 freescale semiconductor 241 table 337. cpmu register summary address name bit 7 6 5 4 3 2 1 bit 0 0x0034 cpmu synr r vcofrq[1:0] syndiv[5:0] w 0x0035 cpmu refdiv r reffrq[1:0] 00 refdiv[3:0] w 0x0036 cpmu postdiv r0 0 0 postdiv[4:0] w 0x0037 cpmuflg r rtif porf lvrf lockif lock ilaf oscif uposc w 0x0038 cpmuint r rtie 00 lockie 00 oscie 0 w 0x0039 cpmuclks r pllsel pstp 00 pre pce rti oscsel cop oscsel w 0x003a cpmupll r0 0 fm1 fm0 00 0 0 w 0x003b cpmurti r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c cpmucop r wcop rsbck 000 cr2 cr1 cr0 w wrtmask 0x003d reservedc pmutest0 r fmcs_reg_ sel 0 cpmu_tes t_gfe 0 cpmu_test _xfc_en 0 fc_force_ en 0 vcofrq2 00 fm_test 0 test_sqw_ osc 0 w 0x003e reservedc pmutest1 r pfd_force_ en 0 cpmu_tes t_clk_en 0 cpmu_test _clk_sel[1] 0 cpmu_tes t_clk_sel[ 0] 0 osc_lcp_ monitor_d isable 0 osc_lcp_e xtsqw_en able 0 pfd_force_ up 0 pfd_force _down 0 w 0x003e reserved cpmufmcs r fmcs_cs[7:0] w 0x003f cpmu armcop r0000000 0 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f0 reserved r0000000 0 w 0x02f1 cpmu lvctl r0 0 0 0 0 lvds lvie lvif w 0x02f2 cpmu apictl r apiclk 00 apies apiea apife apie apif w 0x02f3 cpmuapitr r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w 0x02f4 cpmuapir h r apir15 apir14 apir13 apir1 2 apir11 apir10 apir9 apir8 w 0x02f5 cpmuapirl r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 242 4.38.3.2 register descriptions this section describes all the s12cpm u registers and their individual bits. address order is as listed in figure 337 . 4.38.3.2.1 s12cpmu synthesi zer register (cpmusynr) the cpmusynr register controls the multiplication fa ctor of the pll and selects the vco frequency range. { read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register). el se write has no effect. note writing to this register clears the lock and uposc status bits. note f vco must be within the specified vco frequency lock range. bus frequency f bus must not exceed the specified maximum. the vcofrq[1:0] bits are used to configure the vco gain for optimal stability and lock time. for correct pll operation the vcofrq[1:0] bits have to be selected according to the actual target vcoclk frequency as shown in table 339 . setting the vcofrq[1:0] bits incorrectly can result in a non functi onal pll (no locking and/or insufficient stability). 0x02f6 reservedc pmutest3 r0 lvrt 0 vdd_ext ernal_en 0 regft2 0 regft1 0 regft0 0 regt2 0 regt1 0 regt0 w 0x02f7 reserved r0000000 0 w 0x02f8 cpmu irctrimh r tctrim[4:0] 0 irctrim[9:8] w 0x02f9 cpmu irctriml r irctrim[7:0] w 0x02fa cpmuosc r osce oscbw oscpins_ en oscfilt[4:0] w 0x02fb cpmuprot r0000000 prot w 0x02fc reservedc pmutest2 r0 0 0 lvrs 0 lvrfs 0 lvrxs 000 rcexa w table 338. s12cpmu synthesizer register (cpmusynr) 0x0034 76543210 r vcofrq[1:0] syndiv[5:0] w reset01011111 table 337. cpmu register summary address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved f vco 2 f ref ? syndiv 1 + ?? ? = if pll has locked (lock=1)
mm912_634 advance information, rev. 4.0 freescale semiconductor 243 4.38.3.2.2 s12cpmu reference di vider register (cpmurefdiv) the cpmurefdiv register provides a fine r granularity for the pll multiplier step s when using the external oscillator as reference. read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register). el se write has no effect. note write to this register clears the lock and uposc status bits. the reffrq[1:0] bits are used to configure the internal pll filter for optimal stability and lock time. for correct pll operati on the reffrq[1:0] bits have to be selected according to the actual refclk frequency as shown in table 341 . if irc1m is selected as refclk (osce=0) the pll filter is fixed configured for the 1.0 mhz <= f ref <= 2.0 mhz range. the bits can still be written but will have no effect on the pll filter configuration. for osce=1, setting the reffrq[1:0] bits in correctly can result in a non functional pll (no locking and/or insufficient stabili ty). table 339. vco clock frequency selection vcoclk frequency ranges vcofrq[1:0] 32 mhz <= f vco <= 48 mhz 00 48 mhz < f vco <= 6 4mhz 01 reserved 10 reserved 11 table 340. s12cpmu reference di vider register (cpmurefdiv) 0x0035 76543210 r reffrq[1:0] 00 refdiv[3:0] w reset00001111 f ref f osc refdiv 1 + ?? ------------------------------------ - = if osclcp is enabled (osce=1) if osclcp is disabled (osce=0) f ref f irc 1 m =
mm912_634 advance information, rev. 4.0 freescale semiconductor 244 4.38.3.2.3 s12cpmu po st divider register (cpmupostdiv) the postdiv register contro ls the frequency ratio between the vcoclk and the pllclk. read: anytime write: anytime if pllsel=1. else write has no effect. 4.38.3.2.4 s12cpmu flags register (cpmuflg) this register provides s12cpmu status bits and flags. read: anytime write: refer to each bit for individual write conditions table 341. reference clock frequency selection if osc_lcp is enabled refclk frequency ranges (osce=1) reffrq[1:0] 1.0 mhz <= f ref <= 2.0 mhz 00 2.0 mhz < f ref <= 6.0 mhz 01 6.0 mhz < f ref <= 12.0 mhz 10 f ref >12mhz 11 table 342. s12cpmu post divider register (cpmupostdiv) 0x0036 76543210 r0 0 0 postdiv[4:0] w reset00000011 = unimplemented or reserved table 343. s12cpmu flags register (cpmuflg) 0x0037 76543210 r rtif porf lvrf lockif lock ilaf oscif uposc w reset 0 (182) (183) 00 (184) 00 = unimplemented or reserved note: 182. porf is set to 1 when a power on reset occurs. unaffected by system reset. 183. lvrf is set to 1 when a low voltage reset occurs. unaffected by system reset. set by power on reset. 184. ilaf is set to 1 when an illegal address reset occurs. unaffected by system reset. cleared by power on reset. f pll f vco postdiv 1 + ?? ---------------------------------------- = if pll is locked (lock=1) if pll is not locked (lock=0) f pll f vco 4 -------------- = f bus f pll 2 ------------ = if pll is selected (pllsel=1)
mm912_634 advance information, rev. 4.0 freescale semiconductor 245 note the adaptive oscillator filter uses the vco cl ock as a reference to continuously qualify the external oscillator clock. because of this, the pll is always active and a valid pll configuration is required for the system to work properly. furthe rmore, the adaptive oscillator filter is used to determine the stat us of the external oscillator (reflected in the uposc bit). since this function also relies on the vco clock, loosing pll lock status (lock=0, except for entering pseudo stop m ode) means loosing the oscillator status information as well (uposc=0). table 344. cpmuflg field descriptions field description 7 rtif real time interrupt flag ? rtif is set to 1 at the end of the rti period. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (rtie=1), rtif causes an interrupt request. 0 rti timeout has not yet occurred. 1 rti timeout has occurred. 6 porf power on reset flag ? porf is set to 1 when a power on reset occurs. th is flag can only be cleared by writing a 1. writing a 0 has no effect. 0 power on reset has not occurred. 1 power on reset has occurred. 5 lvrf low voltage reset flag ? lvrf is set to 1 when a low voltage reset occu rs. this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 low voltage reset has not occurred. 1 low voltage reset has occurred. 4 lockif pll lock interrupt flag ? lockif is set to 1 when lock status bit ch anges. this flag can only be cleared by writing a 1. writing a 0 has no effect.if enabled (lockie= 1), lockif causes an interrupt request. 0 no change in lock bit. 1 lock bit has changed. 3 lock lock status bit ? lock reflects the current state of pll lock c ondition. writes have no effe ct. while pll is unlocked (lock=0) fpll is fvco / 4 to protect the system from hi gh core clock frequencies during t he pll stabilization time tlock. 0 vcoclk is not within the desired tolerance of the target frequency. f pll = f vco /4. 1 vcoclk is within the desired tolerance of the target frequency. f pll = f vco /(postdiv+1). 2 ilaf illegal address reset flag ? ilaf is set to 1 when an illegal address reset occurs. refer to mmc chapter for details. this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 illegal address reset has not occurred. 1 illegal address reset has occurred. 1 oscif oscillator interrupt flag ? oscif is set to 1 when uposc status bit changes. this flag can only be cleared by writing a 1. writing a 0 has no effect.if enabled (oscie=1), oscif causes an interrupt request. 0 no change in uposc bit. 1 uposc bit has changed. 0 uposc oscillator status bit ? uposc reflects the status of the oscillator . writes have no effect. while uposc=0 the oscclk going to the mscan module is off. enteri ng full stop mode uposc is cleared. 0 the oscillator is off or oscillation is not qualified by the pll. 1 the oscillator is qualified by the pll.
mm912_634 advance information, rev. 4.0 freescale semiconductor 246 4.38.3.2.5 s12cpmu interrupt en able register (cpmuint) this register enables s12cpmu interrupt requests. read: anytime write: anytime 4.38.3.2.6 s12cpmu cl ock select register (cpmuclks) this register controls s12cpmu clock selection. read: anytime write: 1. only possible if prot=0 (cpmuprot register) in all mcu modes (normal and special mode). 2. all bits in special mode (if prot=0). 3. pllsel, pstp, pre, pce, rtiosc sel: in normal mode (if prot=0). 4. coposcsel: in normal mode (if prot=0) until cpmucop write once is taken. if coposcsel was cleared by uposc=0 (entering full stop mode with coposcsel=1 or insuffic ient oscclk quality), then coposcsel can be set again once. note after writing cpmuclks register, it is strongly recommended to read back cpmuclks register to make sure that write of pllsel, rtioscsel and coposcsel was successful. table 345. s12cpmu interrupt enable register (cpmuint) 0x0038 76543210 r rtie 00 lockie 00 oscie 0 w reset00000000 = unimplemented or reserved table 346. crgint field descriptions field description 7 rtie real time interrupt enable bit 0 interrupt requests from rti are disabled. 1 interrupt will be requested whenever rtif is set. 4 lockie pll lock interrupt enable bit 0 pll lock interrupt requests are disabled. 1 interrupt will be requested whenever lockif is set. 1 oscie oscillator corrupt interrupt enable bit 0 oscillator corrupt interrupt requests are disabled. 1 interrupt will be requested whenever oscif is set. table 347. s12cpmu clock se lect register (cpmuclks) 0x0039 76543210 r pllsel pstp 00 pre pce rti oscsel cop oscsel w reset10000000 = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 247 4.38.3.2.7 s12cpmu pll control register (cpmupll) this register controls the pll functionality. read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register). el se write has no effect. table 348. cpmuclks descriptions field description 7 pllsel pll select bit this bit selects the pllclk as source of the system clocks (cor e clock and bus clock). pllsel can only be set to 0, if uposc=1. uposc= 0 sets the pllsel bit. entering full stop mode sets the pllsel bit. 0 system clocks are derived from oscclk if oscillator is up (uposc=1, f bus = f osc / 2. 1 system clocks are derived from pllclk, f bus = f pll / 2. 6 pstp pseudo stop bit this bit controls the functionality of the oscillator during stop mode. 0 oscillator is disabled in stop mode (full stop mode). 1 oscillator continues to run in stop mode (pseudo stop mode), option to run rti and cop. note: pseudo stop mode allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly incr eased power consumption. note: when starting up the external oscillator (either by progra mming osce bit to 1 or on exit from full stop mode with osce bit is already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t uposc before entering pseudo stop mode. 3 pre rti enable during pseudo stop bit ? pre enables the rti during pseudo stop mode. 0 rti stops running during pseudo stop mode. 1 rti continues running during pseudo stop mode if rtioscsel=1. note: if pre=0 or rtioscsel=0 then the rti will go stat ic while stop mode is active. the rti counter will not be reset. 2 pce cop enable during pseudo stop bit ? pce enables the cop during pseudo stop mode. 0 cop stops running during pseudo stop mode 1 cop continues running during pseudo stop mode if coposcsel=1 note: if pce=0 or coposcsel=0 then the cop will go static while stop mode is active . the cop counter will not be reset. 1 rtioscsel rti clock select ? rtioscsel selects the clock source to the rti. either ircclk or oscclk. changing the rtioscsel bit re-starts the rti timeout period. rtioscsel can only be set to 1, if uposc=1. uposc= 0 clears the rtioscsel bit. 0 rti clock source is ircclk. 1 rti clock source is oscclk. 0 coposcsel cop clock select ? coposcsel selects the clock source to the cop. either ircclk or oscclk. changing the coposcsel bit re-starts the cop timeout period. coposcsel can only be set to 1, if uposc=1. uposc= 0 clears the coposcsel bit. 0 cop clock source is ircclk. 1 cop clock source is oscclk table 349. s12cpmu pll cont rol register (cpmupll) 0x003a 76543210 r0 0 fm1 fm0 0000 w reset00000000
mm912_634 advance information, rev. 4.0 freescale semiconductor 248 note write to this register clears the lock and uposc status bits. note care should be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled. note the frequency modulation (fm1 and fm0) can not be used if the adapti ve oscillator filter is enabled. 4.38.3.2.8 s12cpmu rti cont rol register (cpmurti) this register selects the timeout period for the real time interrupt. the clock source for the rti is either ircclk or oscclk depe nding on the setting of the rtioscsel bit. in stop mode with pstp=1 (pseudo stop mode) and rtioscsel=1 the rti continues to run, else the rti counter halts in stop mode. read: anytime write: anytime note a write to this register starts the rti timeout period. a change of the rtioscsel bit (writing a different value or loosing uposc st atus) restarts the rti timeout period. table 350. cpmupll field descriptions field description 5, 4 fm1, fm0 pll frequency modulation enable bits ? fm1 and fm0 enable frequency modulation on the vcoclk. this is to reduce noise emission. the modulation freque ncy is fref divided by 16. see table 351 for coding. table 351. fm amplitude selection fm1 fm0 fm amplitude / f vco variation 00fm off 01 ? 1% 10 ? 2% 11 ? 4% table 352. s12cpmu rti control register (cpmurti) 0x003b 76543210 r rtdecrtr6rtr5rtr4rtr3rtr2rtr1rtr0 w reset00000000
mm912_634 advance information, rev. 4.0 freescale semiconductor 249 table 353. cpmurti field descriptions field description 7 rtdec decimal or binary divider select bit ? rtdec selects decimal or binary based prescaler values. 0 binary based divider value. see table 354 1 decimal based divi der value. see table 355 6?4 rtr[6:4] real time interrupt prescale rate select bits ? these bits select the prescale rate for the rti. see table 354 and ta b l e 3 5 5 . 3?0 rtr[3:0] real time interrupt modulus counter select bits ? these bits select the modulus count er target value to provide additional granularity. table 354 and table 355 show all possible divide values selectable by the cpmurti register. table 354. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( ? 1) off (185) 2 10 2 11 2 12 2 13 2 14 2 15 2 16 0001 ( ? 2) off 2x2 10 2x2 11 2x2 12 2x2 13 2x2 14 2x2 15 2x2 16 0010 ( ? 3) off 3x2 10 3x2 11 3x2 12 3x2 13 3x2 14 3x2 15 3x2 16 0011 ( ? 4) off 4x2 10 4x2 11 4x2 12 4x2 13 4x2 14 4x2 15 4x2 16 0100 ( ? 5) off 5x2 10 5x2 11 5x2 12 5x2 13 5x2 14 5x2 15 5x2 16 0101 ( ? 6) off 6x2 10 6x2 11 6x2 12 6x2 13 6x2 14 6x2 15 6x2 16 0110 ( ? 7) off 7x2 10 7x2 11 7x2 12 7x2 13 7x2 14 7x2 15 7x2 16 0111 ( ? 8) off 8x2 10 8x2 11 8x2 12 8x2 13 8x2 14 8x2 15 8x2 16 1000 ( ? 9) off 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 ( ? 10) off 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 ( ? 11) off 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 ( ? 12) off 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 ( ? 13) off 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 ( ? 14) off 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16 1110 ( ? 15) off 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 ( ? 16) off 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 note: 185. denotes the default value out of reset.this value should be us ed to disable the rti to ensure future backwards compatibilit y. table 355. rti frequency di vide rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 ) 0000 ( ? 1) 1x10 3 2x10 3 5x10 3 10x10 3 20x10 3 50x10 3 100x10 3 200x10 3 0001 ( ? 2) 2x10 3 4x10 3 10x10 3 20x10 3 40x10 3 100x10 3 200x10 3 400x10 3
mm912_634 advance information, rev. 4.0 freescale semiconductor 250 4.38.3.2.9 s12cpmu cop cont rol register (cpmucop) this register controls the cop (com puter operating properly) watchdog. the clock source for the cop is either ircc lk or oscclk depending on the setting of the coposcsel bit. in stop mode with pstp=1(pseudo stop mode), coposcsel=1 and pce=1 the cop cont inues to run, else the cop counter halts in stop mode. read: anytime write: 1. rsbck: anytime in special mode; write to ?1? but not to ?0? in normal mode 2. wcop, cr2, cr1, cr0: ? anytime in special mode, when wrtmask is 0, otherwise it has no effect ? write once in normal mode, when wr tmask is 0, otherwise it has no effect. ? writing cr[2:0] to ?000? has no effect, but counts for the ?write once? condition. ? writing wcop to ?0? has no effect, but counts for the ?write once? condition. 0010 ( ? 3) 3x10 3 6x10 3 15x10 3 30x10 3 60x10 3 150x10 3 300x10 3 600x10 3 0011 ( ? 4) 4x10 3 8x10 3 20x10 3 40x10 3 80x10 3 200x10 3 400x10 3 800x10 3 0100 ( ? 5) 5x10 3 10x10 3 25x10 3 50x10 3 100x10 3 250x10 3 500x10 3 1x10 6 0101 ( ? 6) 6x10 3 12x10 3 30x10 3 60x10 3 120x10 3 300x10 3 600x10 3 1.2x10 6 0110 ( ? 7) 7x10 3 14x10 3 35x10 3 70x10 3 140x10 3 350x10 3 700x10 3 1.4x10 6 0111 ( ? 8) 8x10 3 16x10 3 40x10 3 80x10 3 160x10 3 400x10 3 800x10 3 1.6x10 6 1000 ( ? 9) 9x10 3 18x10 3 45x10 3 90x10 3 180x10 3 450x10 3 900x10 3 1.8x10 6 1001 ( ? 10) 10 x10 3 20x10 3 50x10 3 100x10 3 200x10 3 500x10 3 1x10 6 2x10 6 1010 ( ? 11) 11 x10 3 22x10 3 55x10 3 110x10 3 220x10 3 550x10 3 1.1x10 6 2.2x10 6 1011 ( ? 12) 12x10 3 24x10 3 60x10 3 120x10 3 240x10 3 600x10 3 1.2x10 6 2.4x10 6 1100 ( ? 13) 13x10 3 26x10 3 65x10 3 130x10 3 260x10 3 650x10 3 1.3x10 6 2.6x10 6 1101 ( ? 14) 14x10 3 28x10 3 70x10 3 140x10 3 280x10 3 700x10 3 1.4x10 6 2.8x10 6 1110 ( ? 15) 15x10 3 30x10 3 75x10 3 150x10 3 300x10 3 750x10 3 1.5x10 6 3x10 6 1111 ( ? 16) 16x10 3 32x10 3 80x10 3 160x10 3 320x10 3 800x10 3 1.6x10 6 3.2x10 6 table 356. s12cpmu cop control register (cpmucop) 0x003c 76543210 r wcop rsbck 000 cr2 cr1 cr0 w wrtmask resetf0000fff reset 00 000 = unimplemented or reserved note: 186. after de-assert of system reset the values are automatically loaded from the flash memory. see device specification for det ails. table 355. rti frequency di vide rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 )
mm912_634 advance information, rev. 4.0 freescale semiconductor 251 when a non-zero value is loaded from flash to cr[2:0] the cop timeout period is started. a change of the coposcsel bit (writing a different value or loosing uposc status) re-starts the cop timeout period. in normal mode the cop timeout period is restar ted if either of these conditions is true: 1. writing a non-zero value to cr[2: 0] (anytime in special mode, once in normal mode) with wrtmask = 0. 2. writing wcop bit (anytime in special mode, once in normal mode) with wrtmask = 0. 3. changing rsbck bit from ?0? to ?1?. in special mode, any write access to cpmucop register restarts the cop timeout period. 4.38.3.2.10 reserved register cpmutest0 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. table 357. cpmucop field descriptions field description 7 wcop window cop mode bit ? when set, a write to the cpmuarmcop register must occur in the last 25% of the selected period. a write during the first 75% of the selected period generates a cop reset. as long as all writes occur during this window, $55 can be written as often as desired. once $aa is written after t he $55, the time-out logic restarts and the user must wait until the next window before writing to cpmuarmcop. table 358 shows the duration of this window for the seven available cop rates. 0 normal cop operation 1 window cop operation 6 rsbck cop and rti stop in active bdm mode bit 0 allows the cop and rti to keep running in active bdm mode. 1 stops the cop and rti counters whenever the part is in active bdm mode. 5 wrtmask write mask for wcop and cr[2:0] bit ? this write-only bit serves as a mask fo r the wcop and cr[2:0] bits while writing the cpmucop register. it is intended for bdm writing the rsbck without changing the content of wcop and cr[2:0]. 0 write of wcop and cr[2:0] has an effect with this write of cpmucop 1 write of wcop and cr[2:0] has no effect with this write of cpmucop. (does not count for ?write once?.) 2?0 cr[2:0] cop watchdog timer rate select ? these bits select the cop timeout rate (see table 358 ). writing a nonzero value to cr[2:0] enables the cop counter and starts the timeout period. a cop counter timeout causes a system reset. this can be avoided by periodically (before ti meout) initializing the cop counter via the cpmuarmcop register. while all of the following four conditions are true the cr[2:0] , wcop bits are ignored and the cop operates at highest timeout period ( 2 24 cycles) in normal cop mode (window cop mode disabled): 1) cop is enabled (cr[2:0] is not 000) 2) bdm mode active 3) rsbck = 0 4) operation in special mode table 358. cop watchdog rates cr2 cr1 cr0 copclk - cycles to timeout (copclk is either ircclk or oscclk depending on the coposcsel bit) 0 0 0 cop disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23 111 2 24
mm912_634 advance information, rev. 4.0 freescale semiconductor 252 read: anytime write: only in special mode table 359. reserved register (cpmutest0) 0x003d 76543210 r fmcs_reg_se l 0 cpmu_test_ gfe 0 cpmu_test_x fc_en 0 fc_force_en 0 vcofrq2 00 fm_test 0 test_sqw_o sc 0 w reset 0 note 1 0000000 1) power on reset clears the crg_test_gfe bit = unimplemented or reserved table 360. cpmutest0 field descriptions field description 7 fmcs_reg_sel fmcs register select bit ? this bit switches either cpmutest1 or cpmufmcs test register to address 0x003e. 0 cpmutest1 register is visible on address 0x003e, fm _cs[7:0] of hardmacro driv en dynamically (triangular) if fm_enable=1. 1 cpmufmcs register is visible on add ress 0x003e, fm_cs[7:0] of hardmacro driven to value of fmcs register. 6 cpmu_test_gfe glitch filter enable test bit ? this bit goes to the pti controller, it is intended to enable the reset pad glitch filter in functional test mode (where it is by default disabled). 0 glitch filter disable request 1 glitch filter enable request 5 cpmu_test_xfc _en xfc test pin enable ? this bit routes the external xfc test pin to the inte rnal filter node. using this test feature make sure that only one source is driving the internal filter node (f c). so for this case write fc_force_en=0, pfd_force_en=1, pfd_force_up=pfd_force_down=0. 0 external xfc test pin not connected to internal filter node 1 external xfc test pin connected to internal filter node 4 fc_force_en fc force enable bit ? this bit allows to force the internal filter node fc to defined values. if fc_force_en=1, reffrq[1] bit (in cpmurefdiv register) selects either 1/2 or 1/3 v ddpll voltage to be driven on fc node. using this test feature make sure that only one source is driving the internal filter node (fc) . so for this case write cpmu_test_xfc_en=0, pfd_force_en=1, pfd_force_up=pfd_force_down=0. 0 internal filter node (fc) not driven from defined values (1/2 or 1/3 v ddpll ) 1 if reffrq[1]=1 then internal filter node (fc) is driven to v ddpll /3. if reffrq[1]=0 then internal filter node (fc) is driven to v ddpll /2. 3 vcofrq2 vco gain bit 2 ? this bit selects together with the vcofrq[1:0] bits of the cpmusynr register the gain of the vtoi converter in the pll. setting vcofrq2-0 al l to 1 is intended for 160mhz vcoclk generation. 1 fm_test fm test amplitude bit ? this bit multiplies fm amplitude determined by fm1,fm0 and cpmufmcs[7:0] by 4. this is to amplify frequency variation on vcoclk when using pll test m odes (pfd_force_en, fc_force_en). a higher frequency variation is easier to measure on tester. 0 fm amplitude multiplied by 1 1 fm amplitude multiplied by 4 0 test_sqw_osc test square wave enable bit ? enables xtal pin digital input data used for oscillator test. 0 xtal pin as digital input disabled 1 xtal pin as digital input enabled
mm912_634 advance information, rev. 4.0 freescale semiconductor 253 4.38.3.2.11 reserved register cpmutest1 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. read: anytime write: only in special mode 4.38.3.2.12 reserved register cpmufmcs table 361. reserved register (cpmutest1) 0x003e 76543210 r pfd_force_e n 0 cpmu_test_c lk_en 0 cpmu_test_c lk_sel[1] 0 cpmu_test_c lk_sel[0] 0 osc_lcp_mo nitor_disable 0 osc_lcp_exts qw_enable 0 pfd_force_u p 0 pfd_force_d own 0 w reset00000000 = unimplemented or reserved table 362. cpmutest1 field descriptions field description 7 pfd_force_en phase detector force enable bit ? this bit breaks the pll feedback loop and allows force of phase detector via pfd_force_up or pfd_force_down bit or cpmu_test_xfc pin or fc_force_en. 0 normal functionality of phase detector using refclk and fbclk. 1 phase detector de-connected from refclk and fbclk (pll loop open). 6 cpmu_test_clk_ en cpmu test clock enable bit ? this bits routes the clock selected by cpmu_t est_clk_sel[1:0] to external pin cpmu_test_clk. 0 cpmu test clock not observable. 1 cpmu test clock observable at external pin. 5, 4 cpmu_test_clk_ sel[1:0] cpmu test clock select bits ? these bits select the cpmu test clock to be observed on external pin cpmu_test_clk for test or characterization purposes. 00 = ircclk, 01=oscclk, 10=vcoclk, 11=vcoclk_div4. 3 osc_lcp_monito r_disable oscillator clock monitor disable bit ? to disable the clock monitor in special single chip mode. 0 clock monitor always enabled with osce=1. 1 clock monitor disabled regardless of osce bit. 2 osc_lcp_extsq w_enable oscillator external square wave enable bit ? drives directly osc_lcp_extsqw _enable input of osclcp hardmacro. 1 pfd_force_up phase detector force up bit ? if pfd_force_en=1, this bits force the pll charge pump to drive the internal filter voltage down, that is vcoclk frequency goes up. using this test feature make sure that only one source is driving the internal filter node (fc). so for this case write xfc_en=fc_force_en=pfd_force_down=0. 0 no effect. 1 if pfd_force_en=1 then the charge pump conti nuously drives internal filter node down. 0 pfd_force_up phase detector force down bit ? if pfd_force_en=1, this bits force the pll char ge pump to drive the internal filter voltage up, that is vcoclk frequency goes down. using this test feature ma ke sure that only one source is driving the internal filter node (fc). so for this case write xfc_en=fc_force_en=pfd_force_up=0. 0 no effect. 1 if pfd_force_en=1 then the charge pump cont inuously drives internal filter node up.
mm912_634 advance information, rev. 4.0 freescale semiconductor 254 read: anytime write: only in special mode 4.38.3.2.13 s12cpmu co p timer arm/reset register (cpmuarmcop) this register is used to restart the cop timeout period. read: always reads $00 write: anytime when the cop is disabled (cr[2:0] = ?000?) writing to this register has no effect. when the cop is enabled by setting cr[2:0] nonzero, the following applies: writing any value other than $55 or $aa causes a cop rese t. to restart the cop timeou t period write $55 followed by a write of $aa. these writes do not need to occur back to back, but the sequence ($55, $aa) must be completed prior to cop end of timeout period to avoid a cop reset. sequences of $55 writes are allowed. when the wcop bit is set, $55 and $aa writes must be done in the last 25% of the sele cted timeout period; writing any value in the first 75% of the selected period will cause a cop reset. 4.38.3.2.14 low voltage control register (cpmulvctl) the cpmulvctl register allows the configur ation of the low-voltage detect features. figure 87. reserved register (cpmufmcs) 0x003e 76543210 r fm_cs[7:0] w reset 00000000 = unimplemented or reserved table 363. cpmufmcs field descriptions field description 7 fm_cs[7:0] frequency modulation amplitude bits ? if fmcs_reg_sel = 1 (cpmutest0 register) then fm_cs[7:0] adds current of 0(fm_cs=$00) to 1 (fm_cs=$ff) times the value determined by fme1, fm0 bits to the vco current. as a result vcoclk frequency will increase. table 364. s12cpmu cpmuarmcop register 0x003f 76543210 r00000000 wbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset00000000 table 365. low voltage control register (cpmulvctl) 0x02f1 76543210 r00000lvds lvie lvif w
mm912_634 advance information, rev. 4.0 freescale semiconductor 255 read: anytime write: lvie and lvif are write anytime, lvds is read only 4.38.3.2.15 autonomous periodical inte rrupt control register (cpmuapictl) the cpmuapictl register allows the configuration of the autonomous periodi cal interrupt features. read: anytime write: anytime reset00000u0u = unimplemented or reserved note: 187. the reset state of lvds and lvif depends on the external supplied vdda level table 366. cpmulvctl field descriptions field description 2 lvds low-voltage detect status bit ? this read-only status bit re flects the voltage level on vdda. writes have no effect. 0 input voltage vdda is above level v lvid or rpm. 1 input voltage vdda is below level v lvia and fpm. 1 lvie low-voltage interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever lvif is set. 0 lvif low-voltage interrupt flag ? lvif is set to 1 when lvds status bit changes. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (lvie = 1), lvif causes an interrupt request. 0 no change in lvds bit. 1 lvds bit has changed. figure 88. autonomous periodical interrupt control register (cpmuapictl) 0x02f2 76543210 r apiclk 00 apies apiea apife apie apif w reset 00000000 = unimplemented or reserved table 365. low voltage control register (cpmulvctl)
mm912_634 advance information, rev. 4.0 freescale semiconductor 256 figure 89. waveform selected on api_extclk pin (apiea=1, apife=1) 4.38.3.2.16 autonomous periodical inte rrupt trimming register (cpmuapitr) the cpmuapitr register configures t he trimming of the api time-out period. table 367. cpmuapictl field descriptions field description 7 apiclk autonomous periodical interrupt clock select bit ? selects the clock source for the api. writable only if apife = 0. apiclk cannot be changed if apife is set by the same write operation. 0 autonomous periodical interrupt clock used as source. 1 bus clock used as source. 4 apies autonomous periodical interrupt external select bit ? selects the waveform at the external pin api_extclk as shown in figure 89 . see device level specification fo r connectivity of api_extclk pin. 0 if apiea and apife are set, at the external pin api_ext clk periodic high pulses are visible at the end of every selected period with the size of half of the minimum period (apir=0x0000 in ta b l e 3 7 1 ). 1 if apiea and apife are set, at the external pin api_e xtclk a clock is visible with 2 times the selected api period. 3 apiea autonomous periodical interrupt external access enable bit ? if set, the waveform selected by bit apies can be accessed externally. see device le vel specification for connectivity. 0 waveform selected by apies can not be accessed externally. 1 waveform selected by apies can be acce ssed externally, if apife is set. 2 apife autonomous periodical interrupt feature enable bit ? enables the api feature and starts the api timer when set. 0 autonomous periodical interrupt is disabled. 1 autonomous periodical interrupt is enabled and timer starts running. 1 apie autonomous periodical interrupt enable bit 0 api interrupt request is disabled. 1 api interrupt will be requested whenever apif is set. 0 apif autonomous periodical interrupt flag ? apif is set to 1 when the in the api c onfigured time has elapsed. this flag can only be cleared by writing a 1. writing a 0 has no effe ct. if enabled (apie = 1), apif causes an interrupt request. 0 api time-out has not yet occurred. 1 api time-out has occurred. apies=0 apies=1 api period api min period / 2
mm912_634 advance information, rev. 4.0 freescale semiconductor 257 read: anytime write: anytime 4.38.3.2.17 autonomous periodical interrupt rate high and low register (cpmuapirh / cpmuapirl) the cpmuapirh and cpmuapirl register s allow the configuration of the autonomous periodical interrupt rate. figure 90. autonomous periodical interrupt trimming register (cpmuapitr) 0x02f3 76543210 r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w reset ffffff00 reset 000000 after de-assert of system reset a value is automatically loaded fr om the flash memory. table 368. cpmuapitr field descriptions field description 7?2 apitr[5:0] autonomous periodical interrupt period trimming bits ? see ta b l e 3 6 9 for trimming effects. the apitr[5:0] value represents a signed number influenc ing the aclk period time. table 369. trimming effect of apitr bit trimming effect apitr[5] increases period apitr[4] decreases period less than apitr[5] increased it apitr[3] decreases period less than apitr[4] apitr[2] decreases period less than apitr[3] apitr[1] decreases period less than apitr[2] apitr[0] decreases period less than apitr[1] figure 91. autonomous pe riodical interrupt rate high register (cpmuapirh) 0x02f4 76543210 r apir15 apir14 apir13 apir1 2 apir11 apir10 apir9 apir8 w reset 00000000 = unimplemented or reserved figure 92. autonomous periodical interrupt rate low register (cpmuapirl) 0x02f5 76543210 r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w reset 00000000
mm912_634 advance information, rev. 4.0 freescale semiconductor 258 read: anytime write: anytime if apife=0. else writes have no effect. the period can be calculated as follows depending on logical value of the apiclk bit: apiclk=0: period = 2* (apir[15:0] + 1) * f aclk apiclk=1: period = 2*(apir[15 :0] + 1) * bus clock period 4.38.3.2.18 reserved register cpmutest3 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. table 370. cpmuapirh / cpmuapirl field descriptions field description 15-0 apir[15:0] autonomous periodical interrupt rate bits ? these bits define the time-out period of the api. see table 371 for details of the effect of the autonomous periodical interrupt rate bits. table 371. selectable autonomous periodical in terrupt periods apiclk apir[15:0] selected period 0 0000 0.2 ms 1 1 when f aclk is trimmed to 10khz. 0 0001 0.4 ms 1 0 0002 0.6 ms 1 0 0003 0.8 ms 1 0 0004 1.0 ms 1 0 0005 1.2 ms 1 0 ..... ..... 0 fffd 13106.8 ms 1 0 fffe 13107.0 ms 1 0 ffff 13107.2 ms 1 1 0000 2 * bus clock period 1 0001 4 * bus clock period 1 0002 6 * bus clock period 1 0003 8 * bus clock period 1 0004 10 * bus clock period 1 0005 12 * bus clock period 1 ..... ..... 1 fffd 131068 * bus clock period 1 fffe 131070 * bus clock period 1 ffff 131072 * bus clock period
mm912_634 advance information, rev. 4.0 freescale semiconductor 259 read: anytime write: only in special mode 4.38.3.2.19 s12cpmu irc1m trim regist ers (cpmuirctrimh / cpmuirctriml) read: anytime write: anytime if prot=0 (cpmuprot register). else write has no effect note writes to these registers while pllsel=1 clears the lock and uposc status bits. table 372. reserved register (cpmutest3) 0x02f6 76543210 r0 lvrt 0 vdd_extern al_en 0 regft2 0 regft1 0 regft0 0 regt2 0 regt1 0 regt0 w reset00000000 power on reset 000000 = unimplemented or reserved table 373. s12cpmu irc1m trim high register (cpmuirctrimh) 0x02f8 15 14 13 12 11 10 9 8 r tctrim[4:0] 0 irctrim[9:8] w reset f f f f 0 0 f f reset 00000011 note: 188. after de-assert of system reset a factory programmed trim val ue is automatically loaded from the flash memory to provide tr immed internal reference frequency f irc1m_trim . table 374. s12cpmu irc1m trim low register (cpmuirctriml) 0x02f9 76543210 r irctrim[7:0] w resetffffffff reset 11111111 note: 189. after de-assert of system reset a factory programmed trim val ue is automatically loaded from the flash memory to provide tr immed internal reference frequency f irc1m_trim .
mm912_634 advance information, rev. 4.0 freescale semiconductor 260 figure 93. irc1m frequency trimming diagram table 375. cpmuirctrimh/l field descriptions field description 15-11 tctrim irc1m temperature coefficient trim bits trim bits for the temperature coefficient (tc) of the irc1m frequency. figure 94 shows the influence of the bits tctrim4:0] on the relationship between frequency and temperature. figure 94 shows an approximate tc variation, relative to the no minal tc of the irc1m (i.e. for tctrim[4:0]=0x00000 or 0x10000). 9-0 irctrim irc1m frequency trim bits ? trim bits for internal reference clock after system reset the factory programmed trim value is automat ically loaded into these registers, resulting in an internal reference frequency f irc1m_trim . see device electrical char acteristics for value of f irc1m_trim . the frequency trimming consists of two different trimming methods: a rough trimming controlled by bits irctrim[9:6] c an be done with frequency leaps of about 6% in average. a fine trimming controlled by the bits ir ctrim[5:0] can be done with frequency leaps of about 0.3% (this trimming determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming values). figure 93 shows the relationship between the trim bits and the resulting irc1m frequency. irctrim[9:0] $000 $1ff irctrim[9:6] irctrim[5:0] irc1m frequency (ircclk) 600 khz 1.5 mhz 1.0 mhz $3ff ......
mm912_634 advance information, rev. 4.0 freescale semiconductor 261 figure 94. influence of tctrim[4:0] on the temperature coefficient note the frequency is not necessarily linear with th e temperature (in most cases it will not be). the above diagram is meant only to give the di rection (positive or negat ive) of the variation of the tc, relative to the nominal tc. setting tctrim[4:0] at 0x00000 or 0x10000 does not mean that the te mperature coefficient will be zero. these two combinations basica lly switch off the tc compensation module, which result in the nominal tc of the irc1m. table 376. tc trimming of the frequency of the irc1m tctrim[4:0] irc1m indicative relative tc variation irc1m indicative frequency drift for relative tc variation 00000 0 (nominal tc of the irc) 0% 00001 -0.27% -0.5% 00010 -0.54% -0.9% 00011 -0.81% -1.3% 00100 -1.08% -1.7% 00101 -1.35% -2.0% 00110 -1.63% -2.2% 00111 -1.9% -2.5% 01000 -2.20% -3.0% 01001 -2.47% -3.4% 01010 -2.77% -3.9% 01011 -3.04 -4.3% 01100 -3.33% -4.7% frequency temperature t c t r im [4 : 0 ] = 0 x 1 1 1 1 1 t c t r i m [ 4 : 0 ] = 0 x 0 1 1 1 1 - 40c 150c tctrim[4:0] = 0x10000 or 0x00000 (nominal tc) 0x00001 0x00010 0x00011 0x00100 0x00101 ... 0x01111 0x11111 ... 0x10101 0x10100 0x10011 0x10010 0x10001 tc increases tc decreases
mm912_634 advance information, rev. 4.0 freescale semiconductor 262 note since the irc1m frequency is not a linear fu nction of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. be aware that the output frequency varies with the tc trimming. a frequency trimming correction is therefore necessa ry. the values provided in ta b l e are typical values at ambient temperature which can vary from device to device. 01101 -3.6% -5.1% 01110 -3.91% -5.6% 01111 -4.18% -5.9% 10000 0 (nominal tc of the irc) 0% 10001 +0.27% +0.5% 10010 +0.54% +0.9% 10011 +0.81% +1.3% 10100 +1.07% +1.7% 10101 +1.34% +2.0% 10110 +1.59% +2.2% 10111 +1.86% +2.5% 11000 +2.11% +3.0% 11001 +2.38% +3.4% 11010 +2.62% +3.9% 11011 +2.89% +4.3% 11100 +3.12% +4.7% 11101 +3.39% +5.1% 11110 +3.62% +5.6% 11111 +3.89% +5.9% table 376. tc trimming of the frequency of the irc1m tctrim[4:0] irc1m indicative relative tc variation irc1m indicative frequency drift for relative tc variation
mm912_634 advance information, rev. 4.0 freescale semiconductor 263 4.38.3.2.20 s12cpmu oscillator register (cpmuosc) this register configures the external oscillator (osclcp). read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register). el se write has no effect. note write to this register clears the lock and uposc status bits. note if the chosen vcoclk-to-oscclk ratio divided by two ((f vco / f osc )/2) is not an integer number, the filter can not be used and the oscfilt[4:0] bits must be set to 0. note the frequency modulation (fm1 and fm0) can not be used if the adapti ve oscillator filter is enabled. 4.38.3.2.21 s12cpmu protect ion register (cpmuprot) this register protects the following clock conf iguration registers from accidental overwrite: cpmusynr, cpmurefdiv, cpmuclks, cpmu pll, cpmuirctrimh /l and cpmuosc table 377. s12cpmu oscillator register (cpmuosc) 0x02fa 76543210 r osce oscbw oscpins_en oscfilt[4:0] w reset00000000 table 378. cpmuosc field descriptions field description 7 osce oscillator enable bit ? this bit enables the external oscillator (osclcp). the upos c status bit in the cpmuflg register indicates when the oscillation is stable and oscclk c an be selected as bus clock or source of the cop or rti. a loss of oscillation will l ead to a clock monitor reset. 0 external oscillator is disabled. refclk for pll is ircclk. 1 external oscillator is enabl ed.clock monitor is enabled. refclk for p ll is external oscilla tor clock divided by refdiv. note: when starting up the external oscillator (either by progra mming osce bit to 1 or on exit from full stop mode with osce bit already 1) the software must wait for a minimu m time equivalent to the startup-time of the external oscillator t uposc before entering pseudo stop mode. 6 oscbw oscillator filter bandwidth bit ? if the vcoclk frequency exceeds 25 mhz wide bandwidth must be selected. the oscillator filter is described in more detail at section 4.38.4.5.2, ?the adaptive oscillator filter 0 oscillator filter bandwidth is narrow (window for expected oscclk edge is one vcoclk cycle). 1 oscillator filter bandwidth is wide (window for expected oscclk edge is three vcoclk cycles). 5 oscpins_en oscillator pins extal and xtal enable bit if osce=1 this read-only bit is set. it can only be cleared with the next reset. enabling the external oscillator reserves the extal and xtal pins exclusively for oscillator application. 0 extal and xtal pins are not reserved for oscillator. 1 extal and xtal pins exclusiv ely reserved for oscillator. 4-0 oscfilt oscillator filter bits ? when using the oscillator a noise filter can be enabled, which filters noise from the incoming external oscillator clock and detects if the external oscillator clock is qualif ied or not (quality status shown by bit uposc). the vcoclk-to-oscclk ratio divided by two ((f vco / f osc )/2) must be an integer value. this value must be written to the oscfilt[4:0] bits to enable t he adaptive oscillator filter. 0x0000 adaptive oscillat or filter disabled. else adaptive oscillator filter enabled]
mm912_634 advance information, rev. 4.0 freescale semiconductor 264 read: anytime write: anytime 4.38.3.2.22 reserved register cpmutest2 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. read: anytime write: only in special mode the reserved register allows several setting to aid to perform dev ice parametric tests this regist er can only be written after writing a $e3 before into this register. table 379. s12cpmu protecti on register (cpmuprot) 0x02fb 76543210 r0000000 prot w reset00000000 table i field description 0 clock configuration registers protection bit ? this bit protects the cl ock configuration registers from accidental overwrite (see list of protected registers above). writing 0x26 to the cpmuprot register clears the prot bit, other write accesses set the prot bit. 0 protection of clock configuration registers is disabled. 1 protection of clock configuration registers is enabled. (see list of protected registers above) table 380. reserved register cpmutest2 0x02fc 76543210 r0 00 lvrs 0 lvrfs 0 lvrxs 000 rcexa w reset00000000 = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 265 4.38.4 functional description 4.38.4.1 phase-locked loop with internal filter (pll) the pll is used to generate a high speed pllclk based on a low frequency refclk. the refclk is by default the ircclk which is trimmed to f irc1m_trim =1.0 mhz. if using the oscillator (osce=1) refclk will be based on oscclk. for increased flexibility, oscclk can be divided in a range of 1 to 16 to generate the reference frequency refclk using th e refdiv[3:0] bits. based on the syndiv[5:0] bits the pll generates the vcoclk by multiplying the reference clock by a 2, 4, 6,... 126, 128. based on the postdiv[4:0] bits the vcoclk can be divided in a range of 1,2, 3, 4, 5, 6,... to 32 to generate the pllclk. table 381. cpmutest2 field descriptions field description 5 lvrs low voltage reset detect vdd status bit ? this read-only status bit reflects the status of the low voltage reset on vdd when core reset disabled for parametric tests. writes have no effect. 0 input voltage v dd is above level v lvra or device is in reduced performance mode (rpm). 1 input voltage v dd is below level v lvra and device is in full performance mode (fpm). 4 lvrfs low voltage reset detect vddf status bit ? this read-only status bit reflects the status of the low voltage reset on vddf when core reset disabled for parametric tests. writes have no effect. 0 input voltage v ddf is above level v lvrfa or device is in rpm. 1 input voltage v ddf is below level v lvrfa and device is in fpm. 3 lvrxs low voltage reset detect vddx status bit ? this read-only status bit reflects the status of the low voltage reset on vddx when core reset disabled for parametric tests. writes have no effect. 0 input voltage v ddx is above level v lvrxa or device is in rpm. 1 input voltage v ddx is below level v lvrxa and device is in fpm. 0 rcexa autonomous periodical interrupt clock (aclk) external access enable bit ? the autonomous periodical interrupt clock (aclk) can be mapped also to an output pin. see section 1 (d evice overview) and section port integration module for details. 0 the autonomous periodical interrupt clock (aclk) is not mapped to an output pin. 1 the autonomous periodical interrupt clock (aclk) is mapped to an output pin if apife is set and apiea=0. f vco 2 f ref ? syndiv 1 + ?? ? = f ref f osc refdiv 1 + ?? ------------------------------------ - = if oscillator is enabled (osce=1) if oscillator is disabled (osce=0) f ref f irc 1 m = f pll f vco postdiv 1 + ?? ---------------------------------------- = if pll is locked (lock=1) if pll is not locked (lock=0) f pll f vco 4 -------------- = f bus f pll 2 ------------ = if pll is selected (pllsel=1)
mm912_634 advance information, rev. 4.0 freescale semiconductor 266 note although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the mcu. several examples of pll divider settings are shown in table 382 . the following rules help to achieve optimum stability and shortest lock time: ? use lowest possible f vco / f ref ratio (syndiv value). ? use highest possible refclk frequency f ref . the phase detector inside the pll compares the feedback clo ck (fbclk = vcoclk/(syndiv+1) with the reference clock (refclk = (irc1m or oscclk)/(refdiv+1)). correction pulses ar e generated based on the phase difference between the two signals. the loop filter alters the dc voltage on the internal fi lter capacitor, based on the width and direction of the correc tion pulse, which leads to a higher or lower vco frequency. the user must select the range of the refclk frequency (reffrq[1:0] bits) and the range of the vcoclk frequency (vcofrq[1:0] bits) to ensure that the correct pll loop bandwidth is set. the lock detector compares the frequencies of the fbclk and th e refclk. therefore the speed of the lock detector is directly proportional to the reference clock frequency. the circuit determines the lock conditi on based on this comparison. if pll lock interrupt requests are enabled, the software can wait for an interrupt request and for instance check the lock bit. if interrupt requests are disabled, software can poll the lock bit continuously (during pll start-up) or at periodic intervals. in either case, only when the lock bit is set, the vcoclk will have stabilized to the programmed frequency. ? the lock bit is a read-only indica tor of the locked state of the pll. ? the lock bit is set when the vco frequency is within the tolerance, ? lock , and is cleared when the vco frequency is out of the tolerance, ? unl . ? interrupt requests can occur if enabled (lockie = 1) when the lock condition changes, toggling the lock bit. 4.38.4.2 startup from reset an example of startu p of clock system from reset is given in figure 95 . figure 95. startup of clock system after reset table 382. examples of pll divider settings f osc refdiv[3:0] f ref reffrq[1:0] syndiv[5:0] f vco vcofrq[1:0] postdiv[4:0] f pll f bus off $00 1.0 mhz 00 $1f 64 mhz 01 $03 16 mhz 8.0 mhz off $00 1.0 mhz 00 $1f 64 mhz 01 $00 64 mhz 32 mhz off $00 1.0 mhz 00 $0f 32 mhz 00 $00 32 mhz 16 mhz 4.0 mhz $00 4.0 mhz 01 $03 32 mhz 01 $00 32 mhz 16 mhz system pllclk reset f vcorst cpu reset state vector fetch, program execution lock postdiv $03 (default target f pll =f vco /4 = 16mhz) f pll increasing f pll =16mhz t lock syndiv $1f (default target f vco =64mhz) $01 f pll =32 mhz example change of postdiv 768 cycles ) (
mm912_634 advance information, rev. 4.0 freescale semiconductor 267 4.38.4.3 stop mode using pllclk as bus clock an example of what happens going into stop mode and exiting stop mode after an interrupt is shown in figure 96 . disable pll lock interrupt (lockie=0) before going into stop mode. figure 96. stop mode using pllclk as bus clock 4.38.4.4 full stop mode using oscillator clock as bus clock an example of what happens going into full stop mode an d exiting full stop mode after an interrupt is shown in figure 97 . disable pll lock interrupt (lockie=0) and oscillator status change interrupt (oscie=0) before going into full stop mode. figure 97. full stop mode using oscillator clock as bus clock 4.38.4.5 extern al oscillator 4.38.4.5.1 enabl ing the external oscillator an example of how to use the oscillator as bus clock is shown in figure 98 . pllclk cpu lock t lock stop instruction execution interrupt continue execution wake-up t stp_rec cpu uposc t lock stop instruction execution interrupt continue execution wake-up t stp_rec core clock select oscclk as core/bus clock by writing pllsel to ?0? pllsel automatically set when going into full stop mode oscclk pllclk
mm912_634 advance information, rev. 4.0 freescale semiconductor 268 figure 98. enabling th e external oscillator 4.38.4.5.2 the adapti ve oscillator filter a spike in the oscillator clock can disturb the function of the modules driven by this clock. the adaptive oscillator filter includes two features: 1. filter noise (spikes) from the incoming external o scillator clock. the filter feature is illustrated in figure 99 . figure 99. noise filtered by the adaptive oscillator filter 2. detect severe noise disturbance on external oscillator clock which can not be filtered and indicate the critical situation to the software by clearing the uposc and lock status bi t and setting the oscif and lockif flag. an example for the detection of critical noise is illustrated in figure 100 figure 100. critical noise detected by the adaptive oscillator filter pllsel osce extal oscclk core enable external oscillator by writing osce bit to one. crystal/resonator starts oscillating uposc uposc flag is set upon successful start of oscillation select oscclk as core/bus clock by writing pllsel to zero clock based on pllclk based on oscclk osce extal oscclk enable external oscillator crystal/resonator starts oscillating uposc osc configure the adaptive oscillator filter filt 0> 0 lock filtered filtered (filtered) osce extal oscclk enable external oscillator crystal/resonator starts oscillating uposc osc configure the adaptive oscillator filter filt 0> 0 lock (filtered) phase shift can not be filtered but detected
mm912_634 advance information, rev. 4.0 freescale semiconductor 269 note if the lock bit is clear due to severe noise disturbance on the external oscillator clock the pllclk is derived from the vco clock (with its actual frequency) divided by four (see also section 4.38.3.2.3, ?s12cpmu post divider register (cpmupostdiv) ). the use of the filter function is only possible if the vcoclk-to-oscclk ratio divided by two ((f vco / f osc )/2) is an integer number. this integer value must be written to the oscfilt[4:0] bits. if enabled, the adaptive oscillato r filter is sampling the incoming external o scillator clock signal (extal) with the vcoclk frequency. using vcoclk, a time window is defined during which an edge of the oscclk is expected. in case of oscbw = 1 the width of this window is three vcoclk cycles, if the oscbw = 0 it is one vcoclk cycle. the noise detection is active for certain combinations of oscfilt[4:0] and oscbw bit settings as shown in table 383 . note if the vcoclk frequency is higher than 25 mhz the wide bandwidth must be selected (oscbw = 1). 4.38.4.6 system clock configurations 4.38.4.6.1 pll engaged internal mode (pei) this mode is the default mode afte r system reset or power-on reset. the bus clock is based on the pllclk, the reference clock for t he pll is internally generated (irc1m). the pll is configured to 64 mhz vcoclk with postdiv set to 0x03. if locked (lock= 1) this results in a pllclk of 16 mhz and a bus clock of 8.0 mhz. the pll can be re-config ured to other bus frequencies. the clock sources for cop and rti are based on t he internal reference clock generator (irc1m). 4.38.4.6.2 pll engaged extern al mode (pee) in this mode, the bus clock is based on the pllclk as well (l ike pei). the reference clock for the pll is based on the external oscillator. the adaptive spike filt er and detection logic which uses the vcoclk to filter and qualify the external oscillator c lock can be enabled. the clock sources for cop and rti can be based on the internal reference clock generator or on the external oscillator clock. this mode can be entered from default mo de pei by performing the following steps: 1. configure the pll for desired bus frequency. 2. optionally the adaptive spike filter and detection logic can be enabled by calculating the integer value for the oscfil[4:0] bits and setting the bandwidth (oscbw) accordingly. 3. enable the external oscillator (osce bit). 4. wait for the pll being locked (lock = 1) and the oscillator to start-up and additionally being qualified if the adaptive oscillator filter is enabled (uposc =1). 5. clear all flags in the cpmuflg register to be able to detect any future status bit change. 6. optionally status interrupts ca n be enabled (cpmuint register). since the adaptive oscillator filt er (adaptive spike filter and detection logic) uses the vcoclk to continuously filter and qua lify the external oscillator clock, loosing pll lock status (lock=0) means loosing t he oscillator status information as well (uposc=0). the impact of loosing t he oscillator status in pee mode is as follows: table 383. noise detection settings oscfilt[4:0] oscbw detection filter 0 x disabled disabled 1 x disabled active 2 or 3 0 active active 1 disabled active >=4 x active active
mm912_634 advance information, rev. 4.0 freescale semiconductor 270 the pllclk is derived from the vco clock (with its act ual frequency) divided by fo ur until the pll locks again. application software needs to be prepared to deal with th e impact of loosing the oscillator status at any time. 4.38.4.6.3 pll bypassed external mode (pbe) in this mode, the bus clock is based on the external oscillator clock. the reference clock for the pll is based on the external oscillator. the adaptive spike f ilter and detection logic can be enabled which us es the vcoclk to filt er and qualify the extern al oscillator clock. the clock sources for cop and rti can be based on the internal reference clock generator or on the external oscillator clock. this mode can be entered from default mo de pei by performing the following steps: 1. make sure the pll configuration is valid. 2. optionally the adaptive spike filter and detection logic can be enabled by calculating the integer value for the oscfil[4:0] bits and setting the bandwidth (oscbw) accordingly. 3. enable the external oscillator (osce bit) 4. wait for the pll being locked (lock = 1) and the oscillator to start-up and additionally being qualified if the adaptive oscillator filter is enabled (uposc=1). 5. clear all flags in the cpmuflg register to be able to detect any status bit change. 6. optionally status interrupts ca n be enabled (cpmuint register). 7. select the oscillator clock (oscclk) as bus clock (pllsel=0) since the adaptive oscillator filt er (adaptive spike filter and detection logic) uses the vcoclk to continuously filter and qua lify the external oscillator clock, loosing pll lock status (lock=0) means loosing t he oscillator status information as well (uposc=0). the impact of loosing t he oscillator status in pbe mode is as follows: ? pllsel is set automatically and the bus clock is switched back to the pllclk. ? the pllclk is derived from the vco clock (with its ac tual frequency) divided by fo ur until the pll locks again. application software needs to be prepared to deal with th e impact of loosing the oscillator status at any time. in the pbe mode, not every noise disturbance can be indi cated by bits lock and uposc (b oth bits are base d on the bus clock domain). there are clock disturbances possible, after which upos c and lock both stay asserted while occasional pauses on the filtered oscclk and resulting bus clock occur. the adaptive sp ike filter is still functional and protects the bus clock fro m frequency overshoot due to spikes on the ex ternal oscillator clock. the filtered os cclk and resulting bus clock will pause unti l the pll has stabilized again. 4.38.5 resets 4.38.5.1 general all reset sources are listed in table 384 . refer to mcu specification for related vector addresses and priorities . 4.38.5.2 description of reset operation upon detection of any reset of table 384 , an internal circ uit drives the reset pin low for 512 pllclk cycles. after 512 pllclk cycles the reset pin is released. the reset generat or of the s12cpmu waits for additi onal 256 pllclk cycles and then samples the reset pin to determine the originating source. table 385 shows which vector will be fetched. table 384. reset summary reset source local enable power-on reset (por) none low voltage reset (lvr) none external pin reset none illegal address reset none clock monitor reset osce bit in cpmuosc register cop reset cr[2:0] in cpmucop register
mm912_634 advance information, rev. 4.0 freescale semiconductor 271 note while system reset is asserted the pllclk runs with the frequency f vcorst . the internal reset of the mcu remains asserted while the reset generat or completes the 768 pl lclk cycles long reset sequence. in case the reset pin is externally driven low for more than these 768 pllclk cycles (external reset), the internal reset remains asserted longer. figure 101. reset timing 4.38.5.2.1 clock monitor reset if the external oscillator is enabled (osce=1) in case of loss of oscillation or the oscillator frequency is below the failure assert frequency f cmfa (see device electrical characterist ics for values), the s12cpmu generates a clock monitor reset. in full stop mode the external oscillator and the clock monitor are disabled. 4.38.5.2.2 computer operating pr operly watchdog (cop) reset the cop (free running watchdog timer) enables the user to che ck that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping the cop fr om timing out. if the cop times out it is an indication that t he software is no longer being executed in the in tended sequence; thus cop reset is generated. the clock source for the cop is either ircc lk or oscclk depending on the setting of the coposcsel bit. in stop mode with pstp=1 (pseudo stop mode), coposcsel=1 and pce=1 the cop cont inues to run, else the cop counter halts in stop mode. three control bits in the cpmucop register al low selection of seven cop time-out periods. when cop is enabled, the program must write $55 and $aa (in this order) to the cpmuarmcop register during the selected time-out period. once this is done, the co p time-out period is restart ed. if the program fails to do this and the cop times out , a cop reset is generated. also, if any value other than $55 or $aa is written, a cop reset is generated. table 385. reset vector selection sampled reset pin (256 cycles after release) oscillator monitor fail pending cop time out pending vector fetch 100 por lvr illegal address reset external pin reset 1 1 x clock monitor reset 101cop reset 0xx por lvr illegal address reset external pin reset ) ( ) pllclk 512 cycles 256 cycles s12_cpmu drives possibly reset driven low ) ( ( reset s12_cpmu releases f vcorst reset pin low reset pin f vcorst
mm912_634 advance information, rev. 4.0 freescale semiconductor 272 windowed cop operation is enabled by setting wcop in the cpmucop register. in this mode , writes to the cpmuarmcop register to clear the cop timer must occur in the last 25% of the selected time-out period. a premature write will immediately reset the part. 4.38.5.3 power-on reset (por) the on-chip por circuitry detects when the internal supply vdd drops below an appropriate voltage level. the por is deasserted, if the internal supply vdd exceeds an appropriate volt age level (voltage levels are not specified in this document because this internal supply is not visible on device pins). 4.38.5.4 low-voltage reset (lvr) the on-chip lvr circuitry detects when one of the supply voltages vdd, vddf or vddx drops below an appropriate voltage level. if lvr is deasserted the mcu is full y operational at the specified maximum speed. the lvr assert and deassert levels for the supply voltage vddx are v lvrxa and v lvrxd and are specified in the device reference manual. 4.38.6 interrupts the interrupt/reset vectors requested by the s12cpmu are listed in table 386 . refer to mcu specification for related vector addresses and priorities. 4.38.6.1 description of interrupt operation 4.38.6.1.1 real time interrupt (rti) the clock source for the rti is either ircclk or oscclk depe nding on the setting of the rtioscsel bit. in stop mode with pstp=1 (pseudo stop mode), rtioscsel=1 and pre=1 the rti continues to run, else the rti counter halts in stop mode. the rti can be used to generate hardware interrupts at a fixed pe riodic rate. if enabled (by setting rtie=1), this interrupt wi ll occur at the rate selected by the cpmurti register. at the end of the rti timeout period the rtif flag is set to one and a new rti timeout period starts immediately. a write to the cpmurti register restarts the rti timeout period. 4.38.6.1.2 pll lock interrupt the s12cpmu generates a pll lock interrupt when the lock condition (lock status bit) of the pll changes, either from a locked state to an unlocked state or vice versa. lock interrupts are lo cally disabled by setting the lockie bit to zero. the pll lock interrupt flag (lockif) is set to 1 when the lock condition has c hanged, and is cleared to 0 by writing a 1 to the lockif bit. 4.38.6.1.3 oscillator status interrupt the adaptive oscillator filter co ntains two different features: 1. filters spikes of the external oscillator clock. 2. qualify the external oscillator clock. when the osce bit is 0, then uposc stays 0. when osce=1 and oscfilt = 0, then t he filter is transpar ent and no spikes are filtered. the uposc bit is then set after the lock bit is set. upon detection of a status change (uposc), that is an unqualified oscillation becomes qualified or vice versa, the oscif flag i s set. going into full stop mode or disabling the oscillator can also cause a status change of uposc. table 386. s12cpmu interrupt vectors interrupt source ccr mask local enable rti timeout interrupt i bit cpmuint (rtie) pll lock interrupt i bit cpmuint (lockie) oscillator status interrupt i bit cpmuint (oscie) low voltage interrupt i bit cpmulvctl (lvie) autonomous periodical interrupt i bit cpmuapictl (apie)
mm912_634 advance information, rev. 4.0 freescale semiconductor 273 also, since the adaptive oscillator filter is based on the pllclk, any change in pl l configuration or any other event which causes the pll lock status to be cleared leads to a lo ss of the oscillator status information as well (uposc=0). oscillator status change interrupts are locally enabled with the oscie bit. note loosing the oscillator status (uposc=0) af fects the clock confi guration of the system (190) . this needs to be dealt with in application software. note: 190. for details please refer to ? 4.38.4.6, ?system clock configurations ?
mm912_634 advance information, rev. 4.0 freescale semiconductor 274 4.39 serial peripheral interface (s12spiv5) preface terminology 4.39.1 introduction the spi module allows a duplex, synchronous, serial communica tion between the mcu and peripheral devices. software can poll the spi status flags or the spi operation can be interrupt driven. 4.39.1.1 glossary of terms 4.39.1.2 features the spi includes these distinctive features: ? master mode and slave mode ? selectable 8 or 16-bit transfer width ? bi-directional mode ? slave select output ? mode fault error flag with cpu interrupt capability ? double-buffered data register ? serial clock with programmable polarity and phase 4.39.1.3 modes of operation the spi functions in two modes: run and stop. ?run mode this is the basic mode of operation. ? stop mode the spi is inactive in stop mode for reduced power consumpti on. if the spi is configured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is configured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. for a detailed description of operating modes, please refer to section 4.39.4.7, ?low power mode options? . 4.39.1.4 block diagram figure 102 gives an overview on the spi architecture. the main parts of the spi are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. spi serial peripheral interface ss slave select sck serial clock mosi master output, slave input miso master input, slave output momi master output, master input siso slave input, slave output
mm912_634 advance information, rev. 4.0 freescale semiconductor 275 figure 102. spi block diagram 4.39.2 external signal description this section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. the sp i module has a total of four external pins. 4.39.2.1 mosi ? master out/slave in pin this pin is used to transmit data out of the spi module when it is conf igured as a master and receiv e data when it is configure d as slave. 4.39.2.2 miso ? master in/slave out pin this pin is used to transmit data out of the spi module when it is configured as a slave and receive data when it is configured as master. spi control register 1 spi control register 2 spi baud rate register spi status register spi data register shifter port control logic mosi sck interrupt control spi msb lsb lsbfe=1 lsbfe=0 lsbfe=0 lsbfe=1 data in lsbfe=1 lsbfe=0 data out baud rate generator prescaler bus clock counter clock select sppr 3 3 spr baud rate phase + polarity control master slave sck in sck out master baud rate slave baud rate phase + polarity control control control cpol cpha 2 bidiroe spc0 2 shift sample clock clock modf spif sptef spi request interrupt ss
mm912_634 advance information, rev. 4.0 freescale semiconductor 276 4.39.2.3 ss ? slave select pin this pin is used to output the select signal from the spi module to another peripheral with which a data transfer is to take pl ace when it is configured as a master and it is used as an input to receive the slave se lect signal when the spi is configured as s lave. 4.39.2.4 sck ? serial clock pin in master mode, this is the synchronous output clock. in slave mode, this is the synchronous input clock. 4.39.3 memory map and register definition this section provides a detailed description of address space and registers used by the spi. 4.39.3.1 module memory map the memory map for the spi is given in figure 387 . the address listed for each register is the sum of a base address and an address offset. the base address is defined at the soc level and t he address offset is defined at the module level. reads from the reserved bits return zeros and writes to the reserved bits have no effect. 4.39.3.2 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. table 387. spi re gister summary register name bit 7654321bit 0 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w spicr2 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w spisr rspif0sptefmodf0000 w spidrh r r15 r14 r13 r12 r11 r10 r9 r8 t15 t14 t13 t12 t11 t10 t9 t8 w spidrl rr7r6r5r4r3r2r1r0 t7 t6 t5 t4 t3 t2 t1 t0 w reserved r w reserved r w = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 277 4.39.3.2.1 spi control register 1 (spicr1) read: anytime write: anytime table 388. spi control register 1 (spicr1) 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset00000100 table 389. spicr1 field descriptions field description 7 spie spi interrupt enable bit ? this bit enables spi interrupt requests, if spif or modf status flag is set. 0 spi interrupts disabled. 1 spi interrupts enabled. 6 spe spi system enable bit ? this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disabled and forced into idle st ate, status bits in spisr register are reset. 0 spi disabled (lower power consumption). 1 spi enabled, port pins are dedicated to spi functions. 5 sptie spi transmit interrupt enable ? this bit enables spi interrupt requests, if sptef flag is set. 0 sptef interrupt disabled. 1 sptef interrupt enabled. 4 mstr spi master/slave mode select bit ? this bit selects whether the spi operates in master or slave mode. switching the spi from master to slave or vice versa forces the spi system into idle state. 0 spi is in slave mode. 1 spi is in master mode. 3 cpol spi clock polarity bit ? this bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 active-high clocks selected. in idle state sck is low. 1 active-low clocks selected. in idle state sck is high. 2 cpha spi clock phase bit ? this bit is used to select the spi clock format. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 sampling of data occurs at odd edges (1,3,5,...) of the sck clock. 1 sampling of data occurs at even edges (2,4,6,...) of the sck clock. 1 ssoe slave select output enable ? the ss output feature is enabled only in master mode, if modfen is set, by asserting the ssoe as shown in table 390 . in master mode, a change of this bit will abo rt a transmission in progress and force the spi system into idle state. 0 lsbfe lsb-first enable ? this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in the highest bit position. in master mode, a change of this bit will abort a transmission i n progress and force the spi system into idle state. 0 data is transferred most significant bit first. 1 data is transferred least significant bit first.
mm912_634 advance information, rev. 4.0 freescale semiconductor 278 4.39.3.2.2 spi control register 2 (spicr2) read: anytime write: anytime; writes to the reserved bits have no effect table 390. ss input / output selection modfen ssoe master mode slave mode 00 ss not used by spi ss input 01 ss not used by spi ss input 10 ss input with modf feature ss input 11 ss is slave select output ss input table 391. spi control register 2 (spicr2) 76543210 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w reset00000000 = unimplemented or reserved table 392. spicr2 field descriptions field description 6 xfrw transfer width ? this bit is used for selecting the data transfer widt h. if 8-bit transfer width is selected, spidrl becomes the dedicated data register and spidrh is unused. if 16-bit transfer width is selected, spidrh and spidrl form a 16-bit data register. please refer to section 4.39.3.2.4, ?spi status register (spisr) for information about tran smit/receive data handling and the interrupt flag clearing mechanism. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 8-bit transfer width (n = 8) (191) 1 16-bit transfer width (n = 16) (191) 4 modfen mode fault enable bit ? this bit allows the modf failure to be detec ted. if the spi is in master mode and modfen is cleared, then the ss port pin is not used by the spi. in slave m ode, the ss is available only as an input regardless of the val ue of modfen. for an overview on the impact of the mo dfen bit on the ss port pin configuration, refer to table 390 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0ss port pin is not used by the spi. 1ss port pin with modf feature. 3 bidiroe output enable in the bidirectional mode of operation ? this bit controls the mosi and miso output buffer of the spi, when in bidirectional mode of operation (spc0 is set). in master mode, this bit controls the output buffer of the mosi port, in slave mode it controls the output buffer of the miso port. in master mode, with spc0 set, a change of this bit will abort a transmission in progress and force the spi into idle state. 0 output buffer disabled. 1 output buffer enabled. 1 - reserved ? for internal use 0 spc0 serial pin control bit 0 ? this bit enables bidirectional pi n configurations as shown in table 393 . in master mode, a change of this bit will abort a transmission in progr ess and force the spi system into idle state. note: 191. n is used later in this document as a placeholder for the selected transfer width.
mm912_634 advance information, rev. 4.0 freescale semiconductor 279 4.39.3.2.3 spi baud ra te register (spibr) read: anytime write: anytime; writes to the reserved bits have no effect the baud rate divisor equation is as follows: baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 103 the baud rate can be calculated with the following equation: baud rate = busclo ck / baudratedivisor eqn. 104 note for maximum allowed baud rates, please refer to the spi electrical specification in the electricals chapter of this data sheet. table 393. bidirectional pin configurations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in bidirectional 1 0 slave in mosi not used by spi 1 slave i/o table 394. spi baud rate register (spibr) 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset00000000 = unimplemented or reserved table 395. spibr field descriptions field description 6?4 sppr[2:0] spi baud rate preselection bits ? these bits specify the spi baud rates as shown in table 396 . in master mode, a change of these bits will abort a transmission in prog ress and force the spi system into idle state. 2?0 spr[2:0] spi baud rate selection bits ? these bits specify the spi baud rates as shown in table 396 . in master mode, a change of these bits will abort a transmi ssion in progress and force the spi system into idle state. table 396. example spi baud rate selection (25 mhz us clock) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 0 0 0 0 0 0 2 12.5 mbit/s 0 0 0 0 0 1 4 6.25 mbit/s 0 0 0 0 1 0 8 3.125 mbit/s 0 0 0 0 1 1 16 1.5625 mbit/s
mm912_634 advance information, rev. 4.0 freescale semiconductor 280 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 0 0 1 0 0 0 4 6.25 mbit/s 0 0 1 0 0 1 8 3.125 mbit/s 0 0 1 0 1 0 16 1.5625 mbit/s 0 0 1 0 1 1 32 781.25 kbit/s 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 mbit/s 0 1 0 0 0 1 12 2.08333 mbit/s 0 1 0 0 1 0 24 1.04167 mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 mbit/s 0 1 1 0 0 1 16 1.5625 mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 mbit/s 1 0 0 0 0 1 20 1.25 mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 mbit/s 1 0 1 0 0 1 24 1.04167 mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s table 396. example spi baud rate selection (25 mhz us clock) (continued) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
mm912_634 advance information, rev. 4.0 freescale semiconductor 281 4.39.3.2.4 spi status register (spisr) read: anytime write: has no effect 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s table 397. spi status register (spisr) 76543210 r spif 0 sptef modf 0 0 0 0 w reset00100000 = unimplemented or reserved table 396. example spi baud rate selection (25 mhz us clock) (continued) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
mm912_634 advance information, rev. 4.0 freescale semiconductor 282 table 398. spisr field descriptions field description 7 spif spif interrupt flag ? this bit is set after received data has been transfe rred into the spi data register. for information about clearing spif flag, please refer to ta b l e . 0 transfer not yet complete. 1 new data copied to spidr. 5 sptef spi transmit empty interrupt flag ? if set, this bit indicates that the transmit data register is empty. for information about clearing this bit and placing data into th e transmit data register, please refer to table . 0 spi data register not empty. 1 spi data register empty. 4 modf mode fault flag ? this bit is set if the ss input becomes low while t he spi is configured as a master and mode fault detection is enabled, modfen bit of spicr2 register is set. refer to modfen bit description in section 4.39.3.2.2, ?spi control register 2 (spicr2)? . the flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to the spi control register 1. 0 mode fault has not occurred. 1 mode fault has occurred. table 399. spif interrupt flag clearing sequence xfrw bit spif interrupt flag clearing sequence 0 read spisr with spif = 1 then read spidrl 1 read spisr with spif = 1 then byte read spidrl (192) or byte read spidrh (193) byte read spidrl or word read (spidrh:spidrl) note: 192. data in spidrh is lost in this case. 193. spidrh can be read repeatedly without any effect on spif. spi f flag is cleared only by the read of spidrl after reading spi sr with spif = 1. table 400. sptef interrupt flag clearing sequence xfrw bit sptef interrupt flag clearing sequence 0 read spisr with sptef = 1 then write to spidrl (194) 1 read spisr with sptef = 1 then byte write to spidrl (194)(195) or byte write to spidrh (194)(196) byte write to spidrl (194) or word write to (spidrh:spidrl) (194) note: 194. any write to spidrh or spidrl with sptef = 0 is effectively ignored. 195. data in spidrh is undefined in this case. 196. spidrh can be written repeatedly without any effect on sptef. sptef flag is cleared only by writing to spidrl after reading spisr with sptef = 1.
mm912_634 advance information, rev. 4.0 freescale semiconductor 283 4.39.3.2.5 spi data regist er (spidr = spidrh:spidrl) read: anytime; read data only valid when spif is set write: anytime the spi data register is both the input and ou tput register for spi data. a write to th is register allows data to be queued and transmitted. for an spi configured as a master, queued data is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag sptef in the spisr regi ster indicates when the spi data register is ready to accept new data. received data in the spidr is valid when spif is set. if spif is cleared and data has been received, the received data is transferred from the receive shift register to the spidr an d spif is set. if spif is set and not serviced, and a second data value has been re ceived, the second received data is kept as valid data in t he receive shift register until the start of another tr ansmission. the data in the spidr does not change. if spif is set and valid data is in the receive shift register, and spif is serviced before the start of a third transmission, the data in the receive shift register is transfe rred into the spidr and spif remains set (see figure 105 ). if spif is set and valid data is in the receive shift register , and spif is serviced after the start of a third transmission, t he data in the receive shift register has become invalid and is not transferred into the spidr (see figure 106 ). figure 105. reception with spif serviced in time table 401. spi data register high (spidrh) 76543210 r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 reset00000000 table 402. spi data re gister low (spidrl) 76543210 r r7 r6 r5 r4 r3 r2 r1 r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset00000000 receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b = unspecified = reception in progress
mm912_634 advance information, rev. 4.0 freescale semiconductor 284 figure 106. reception with spif serviced too late 4.39.4 functional description the spi module allows a duplex, synchronous, serial communica tion between the mcu and peripheral devices. software can poll the spi status flags or sp i operation can be interrupt driven. the spi system is enabled by se tting the spi enable (spe) bit in spi control register 1. while spe is set, the four associated spi port pins are dedicated to the spi function as: ? slave select (ss ) ? serial clock (sck) ? master out/slave in (mosi) ? master in/slave out (miso) the main element of the spi system is the spi data register. the n-bit (197) data register in the master and the n-bit (197) data register in the slave are linked by the mosi and miso pins to form a distributed 2n-bit (197) register. when a data transfer operation is performed, this 2n-bit (197) register is serially shifted n (197) bit positions by the s-clock from the master, so data is exchanged between the master and the slave. data written to the master spi data re gister becomes the output data for the slave, and data read from the master spi data register after a transfer operation is the input data from the slave. a read of spisr with sptef = 1 followed by a write to spidr put s data into the transmit data register. when a transfer is complete and spif is cleared, received data is moved into the receive data register. this data register acts as the spi receive data register for reads and as the spi trans mit data register for writes. a common spi da ta register address is shared for read ing data from the read data buffer and for writing data to the transmit data register. the clock phase control bit (cpha) and a clock polarity control bi t (cpol) in the spi control regi ster 1 (spicr1) select one of four possible clock formats to be used by the spi system. the cpol bit simply select s a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered sck edges or on even numbered sck edges (see section 4.39.4.3, ?transmission formats? ). the spi can be configured to operate as a master or as a slave. when the mstr bit in spi control register1 is set, master mode is selected, when the mstr bit is clear, slave mode is selected. note: 197. n depends on the selected transfer width, refer to section 4.39.3.2.2, ?spi control register 2 (spicr2) note a change of cpol or mstr bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b lost = unspecified = reception in progress
mm912_634 advance information, rev. 4.0 freescale semiconductor 285 4.39.4.1 master mode the spi operates in master mode when the ms tr bit is set. only a master spi module can initiate transmissions. a transmission begins by writing to the master spi data register. if the shift r egister is empty, data immediately transfers to the shift regi ster. data begins shifting out on the mosi pin under the control of the serial clock. ? serial clock the spr2, spr1, and spr0 baud rate selection bits, in conjunction with the sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate register, control the baud rate generator and determine the speed of the transmission. the sck pin is the spi clock output. through the sck pin, the baud rate generator of the master controls the shift register of the slave peripheral. ? mosi, miso pin in master mode, the function of the serial data output pin (mosi) and the serial data input pin (miso) is determined by the spc0 and bidiroe control bits. ?ss pin if modfen and ssoe are set, the ss pin is configured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. if modfen is set and ssoe is cleared, the ss pin is configured as input for detecting mode fault error. if the ss input becomes low this indicates a mode fault error where another ma ster tries to drive the mosi and sck lines. in this case, the spi immediately switches to slave m ode, by clearing the mstr bit and also disables the slave output buffer miso (or siso in bidirectional mode). so the result is that all outputs are disabled and sck, mosi, and miso are inputs. if a transmission is in progress when the mode fault occurs, the tran smission is aborted and the spi is forced into idle state. this mode fault error also sets the mode fault (modf) flag in the spi status register (spisr ). if the spi interrupt enable bit (spie) is set when the modf flag becomes set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master occurs, there is a half sck-cycl e delay. after the dela y, sck is started within the master. the rest of the transfer operation differs slightly, depending on the clock format specified by the spi clock phase bit, cpha, in spi control register 1 (see section 4.39.4.3, ?transmission formats?) . note a change of the bits cpol, cpha, ssoe, lsbfe, xfrw, modfen, spc0, or bidiroe with spc0 set, sppr2-sppr0 and spr2-spr0 in master mode will abo rt a transmission in progress and force the spi into idle state. the remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. 4.39.4.2 slave mode the spi operates in slave mode when the mstr bit in spi control register 1 is clear. ? serial clock in slave mode, sck is the spi clock input from the master. ? miso, mosi pin in slave mode, the function of the se rial data output pin (miso) and serial data input pin (mosi) is determined by the spc0 bit and bidiroe bit in spi control register 2. ?ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the seri al data output pin, if ss is high (not selected), the serial data output pin is high impedance, and, if ss is low, the first bit in the spi data register is driven out of the serial data output pin. also, if the slave is not selected (ss is high), then the sck input is ignored and no in ternal shifting of the spi shift register occurs. although the spi is capable of duplex operation, some spi per ipherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin. note when peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the sa me system slave?s serial data output line. as long as no more than one slave device driv es the system slave?s serial data output lin e, it is possible for several slaves t o receive the same transmission from a master , although the master would not receive retu rn information from all of the receiving slaves.
mm912_634 advance information, rev. 4.0 freescale semiconductor 286 if the cpha bit in spi control register 1 is clear, odd numbered edges on the sck in put cause the data at the serial data input pin to be latched. even numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. if the cpha bit is set, even numbered edges on the sck input ca use the data at the serial data input pin to be latched. odd numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the first edge is used to get the first data bi t onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the first bit of the spi data is driven out of the serial data output pin. after the nth (198) shift, the transfer is considered complete and the received data is transferred into the spi data register. to indicate transfer is complete, the s pif flag in the spi status register is set. note: 198. n depends on the selected transfer width, refer to section 4.39.3.2.2, ?spi control register 2 (spicr2) note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, or bidiroe with spc0 set in slave mode will corrupt a transmission in progress and must be avoided. 4.39.4.3 transmission formats during an spi transmission, data is transmi tted (shifted out serially) and received (shifted in serially) simultaneously. the s erial clock (sck) synchronizes shif ting and sampling of the information on the two serial data lines. a slave select line allows sele ction of an individual slave spi device; slave devices that are no t selected do not interfere with spi bus activities. optionally, on a master spi device, the slave sele ct line can be used to indicate multiple-master bus contention. figure 107. master/slave transfer block diagram 4.39.4.3.1 clock phase and polarity controls using two bits in the spi control register 1, software select s one of four combinations of serial clock phase and polarity. the cpol clock polarity control bi t specifies an active high or low clock and has no significant effect on the transmission for mat. the cpha clock phase control bit selects one of tw o fundamentally different transmission formats. clock phase and polarity should be identical for the master spi dev ice and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a ma ster device to communicate with peripheral slaves having different requirements. 4.39.4.3.2 cpha = 0 transfer format the first edge on the sck line is used to clock the first data bi t of the slave into the master and the first data bit of the m aster into the slave. in some peripherals, the first bit of the slave?s data is available at the slave?s dat a out pin as soon as the slave is selected. in this format, the first sc k edge is issued a half cycle after ss has become low. a half sck cycle later, the second edge appears on the sck line. when this second edge occurs, the value previously latched from the serial data input pin is shifted into the l sb or msb of the shift register, depending on lsbfe bit. after this second edge, the next bit of the spi master data is tr ansmitted out of the serial data output pin of the master to t he serial input pin on the slave. this process continues for a total of 16 edges on the sck line, with data being latched on odd numbered edges and shifted on even numbered edges. shift register shift register baud rate generator master spi slave spi mosi mosi miso miso sck sck ss ss v dd
mm912_634 advance information, rev. 4.0 freescale semiconductor 287 data reception is double buffered. data is shifted serially in to the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n (199) (last) sck edges: ? data that was previously in the master spi data register should now be in t he slave data register and the data that was in the slave data register should be in the master. ? the spif flag in the spi status register is set, indicating that the transfer is complete. figure 108 is a timing diagram of an spi transfer where cpha = 0. sck waveforms are shown for cpol = 0 and cpol = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso , and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave and the mosi signal is the output from the master. the ss pin of the master must be either high or reconfig ured as a general-purpose output not affecting the spi. note: 199. n depends on the selected transfer width, refer to section 4.39.3.2.2, ?spi control register 2 (spicr2) figure 108. spi clock format 0 (cpha = 0), with 8-bit transfer width selected (xfrw = 0) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
mm912_634 advance information, rev. 4.0 freescale semiconductor 288 figure 109. spi clock format 0 (cpha = 0), wi th 16-bit transfer width selected (xfrw = 1) in slave mode, if the ss line is not deasserted between the successive transmi ssions then the content of the spi data register is not transmitted; instead the last rece ived data is transmitted. if the ss line is deasserted for at least minimum idle time (half sck cycle) between successive transmissions, then the co ntent of the spi data register is transmitted. in master mode, with slave select output enabled the ss line is always deasserted and rea sserted between successive transfers for at least minimum idle time. 4.39.4.3.3 cpha = 1 transfer format some peripherals require the first sck edge before the first da ta bit becomes available at the data out pin, the second edge clocks data into the system. in th is format, the first sck edge is issued by se tting the cpha bit at the begi nning of the n (200) -cycle transfer operation. the first edge of sck occurs immediately after the half sck clock cycle synchronization delay. this first edge commands the slave to transfer its first data bit to the serial data input pin of the master. a half sck cycle later, the second edge appears on the sck pin. this is the latching edge for both the master and slave. when the third edge occurs, the value previous ly latched from the serial data input pin is shifted into the lsb or msb of the s pi shift register, depending on lsbfe bit. after this edge, the next bit of the master data is coupled out of the serial data outp ut pin of the master to the serial input pin on the slave. this process continues for a total of n edges on the sck line with data being latched on even numbered edges and shifting takin g place on odd numbered edges. note: 200. n depends on the selected transfer width, please refer to section 4.39.3.2.2, ?spi control register 2 (spicr2) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0) lsb first (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12bit 13 bit 14
mm912_634 advance information, rev. 4.0 freescale semiconductor 289 data reception is double buffered, data is serially shifted in to the spi shift register durin g the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n sck edges: ? data that was previously in the spi data register of the master is now in the data register of the slave, and data that was in the data register of th e slave is in the master. ? the spif flag bit in spisr is set indi cating that the transfer is complete. figure 110 shows two clocking variations for cpha = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and th e slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the ss pin of the master must be either high or reconfigured as a general-purpose output not affecting the spi. figure 110. spi clock format 1 (cpha = 1), with 8-bit transfer width selected (xfrw = 0) t l t t for t t , t l , t l minimum 1/2 sck t i t l if next transfer begins here begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t l = minimum leading time before the first sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
mm912_634 advance information, rev. 4.0 freescale semiconductor 290 figure 111. spi clock format 1 (cpha = 1), wit h 16-bit transfer width selected (xfrw = 1) the ss line can remain active low between successive transfers (can be tied low at all times). this format is sometimes preferred in systems having a single fix ed master and a single slave th at drive the miso data line. back-to-back transfer s in master mode in master mode, if a transmission has completed and new data is available in the spi data register, this data is sent out immediately without a trailing and minimum idle time. the spi interrupt request flag ( spif) is common to both the master and slave modes. spif gets set one half sck cycle after the last sck edge. 4.39.4.4 spi baud rate generation baud rate generation consists of a series of divider stages. si x bits in the spi baud rate register (sppr2, sppr1, sppr0, spr2, spr1, and spr0) determine the divisor to the spi module clock which results in the spi baud rate. the spi clock rate is determin ed by the product of the value in the baud rate pres election bits (sppr2? sppr0) and the value in the baud rate selection bits (spr2?spr0). the module clock divisor equation is shown in equation 112 . baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 112 when all bits are clear (the default condit ion), the spi module clock is divided by 2. when the selection bits (spr2?spr0) are 001 and the presel ection bits (sppr2?sppr0) ar e 000, the module clock divisor becomes 4. when the selection bits are 010, the module clock divisor becomes 8, etc. when the preselection bits are 001, the divi sor determined by the selection bits is mu ltiplied by 2. when the preselection bits are 010, the divisor is multiplied by 3, etc. see table 396 for baud rate calculations for all bit conditions, based on a 25 mhz bus clock. the two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0) lsb first (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sc k edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12bit 13 bit 14
mm912_634 advance information, rev. 4.0 freescale semiconductor 291 the baud rate generator is activated only wh en the spi is in master mode and a serial transfer is taking place. in the other ca ses, the divider is disabled to decrease i dd current. note for maximum allowed baud rates, please refer to the spi electrical specification in the electricals chapter of this data sheet. 4.39.4.5 special features 4.39.4.5.1 ss output the ss output feature automat ically drives the ss pin low during transmission to select external devices and drives it high during idle to deselect exte rnal devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in master mode during normal spi operation by asserting ssoe and modfen bit as shown in table 390 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a mult imaster system because the mode fault feature is not available for detecting system errors between masters. 4.39.4.5.2 bidirectional mode (momi or siso) the bidirectional mode is selected when the spc0 bit is set in spi control register 2 (see table 403 ). in this mode, the spi uses only one serial data pin for the interface with external device(s) . the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (momi) pin for the master mode, and the mi so pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pi n in slave mode are not used by the spi. the direction of each serial i/o pin depends on the bidiroe bit. if the pin is configured as an output, serial data from the sh ift register is driven out on the pi n. the same pin is also the serial input to the shift register. ? the sck is output for the master mode and input for the slave mode. ?the ss is the input or output for the master mode, and it is always the input for the slave mode. ? the bidirectional mode does not affect sck and ss functions. note in bidirectional master mode, with mode f ault enabled, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirectional mode and miso is not used by the spi. if a mode fault occu rs, the spi is automatically switched to slave mode. in th is case miso becomes occupied by the spi and mosi is not used. this must be considered, if the miso pin is used for another purpose. table 403. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out bidiroe
mm912_634 advance information, rev. 4.0 freescale semiconductor 292 4.39.4.6 error conditions the spi has one error condition: mode fault error 4.39.4.6.1 mode fault error if the ss input becomes low while the spi is configured as a master , it indicates a system error where more than one master may be trying to drive the mosi and sck lines simultaneously. this cond ition is not permitted in normal operation, the modf bit in the spi status register is set automati cally, provided the modfen bit is set. in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf remains cl eared. in case the spi system is configured as a slave, the ss pin is a dedicated input pin. mode fault error doesn?t occur in slave mode. if a mode fault error occurs, the spi is s witched to slave mode, with the exception that the slave outp ut buffer is disabled. s o sck, miso, and mosi pins are forced to be high impedance inputs to avoid any possibility of co nflict with another output driver . a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in the bidirectional mode for a spi system configured in master m ode, output enabl e of the momi (mosi in bidirectional mode) is cleared if it was set. no mode fault error occurs in the bidirectional mode for spi system configured in slave mode. the mode fault flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi co ntrol register 1. if the mode fault flag is cleared, the spi becomes a normal master or slave again. note if a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 4.39.4.7 low power mode options 4.39.4.7.1 spi in run mode in run mode with th e spi system enable (spe) bit in t he spi control register clear, the spi system is in a low-power, disabled state. spi registers remain acce ssible, but clocks to the core of this module are disabled. 4.39.4.7.2 spi in stop mode stop mode is dependent on the system. the spi enters stop mode when the module clock is disabled (held high or low). if the spi is in master mode and exchanging data when the cpu enters stop mode, the transmission is fr ozen until the cpu exits stop mode. after stop, data to and from the external spi is exc hanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. 4.39.4.7.3 reset the reset values of registers and signals are described in section 4.39.3, ?memory map and register definition? , which details the registers and their bit fields. ? if a data transmission occurs in slave mode after reset without a write to spidr, it will transmit garbage, or the data last received from the master before the reset. ? reading from the spidr after reset will always read zeros. 4.39.4.7.4 interrupts the spi only originates interrupt requests when spi is enabled (spe bit in spicr1 set). the following is a description of how t he spi makes a request and how the mcu should acknowledge that reque st. the interrupt vector offset and interrupt priority are chip dependent. the interrupt flags modf, spif, and sptef are lo gically ored to generate an interrupt request. 4.39.4.7.4.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be co nfigured for the modf feature (see table 390 ). after modf is set, the current transfer is aborted and the following bit is changed:
mm912_634 advance information, rev. 4.0 freescale semiconductor 293 mstr = 0, the master bit in spicr1 resets. the modf interrupt is refl ected in the status register modf flag. clearing the flag will also clear the interrupt. this interru pt will stay active while the modf flag is set. modf has an automatic clearing proce ss which is described in section 4.39.3.2.4, ?spi status register (spisr)? . 4.39.4.7.4.2 spif spif occurs when new data has been received and copied to the spi data register. after spif is set, it does not clear until it is serviced. spif has an automatic cleari ng process, which is described in section 4.39.3.2.4, ?spi status register (spisr)? . 4.39.4.7.4.3 sptef sptef occurs when the spi data register is ready to accept new data. after sptef is set, it d oes not clear until it is serviced . sptef has an automatic clearing pr ocess, which is described in section 4.39.3.2.4, ?spi status register (spisr)? . 4.39.5 initialization/a pplication information
mm912_634 advance information, rev. 4.0 freescale semiconductor 294 4.40 64 kbyte flash module (s12ftmrc64k1v1) 4.40.1 introduction the module implements the following: ? kbytes of p-flash (program flash) memory ? kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowin g for field reprogramming without requiring external high volta ge sources for program or erase operations. the flash module incl udes a memory controller that ex ecutes commands to modify flash memory contents. the user interface to the memory co ntroller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the exec ution of a command before the fccob regist er can be written to with a new command. caution a flash word or phrase must be in the eras ed state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is possible to read from p-flash memory while some comm ands are executing on d-flash memory. it is not possible to read from d-flash memory while a command is executing on p-fl ash memory. simultaneous p-flash and d-flash operations are discussed in section 4.40.4.4 . both p-flash and d-flash memories are im plemented with error correction codes (ecc) t hat can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementati on requires that programming be done on an aligned 8 byte basis (a flash phrase). since p-flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 4.40.1.1 glossary command write sequence ? an mcu instruction sequence to execute built-i n algorithms (including program and erase) on the flash memory. d-flash memory ? the d-flash memory constitutes the nonvolatile memory store for data. d-flash sector ? the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64 byte rows for a total of 256 bytes. nvm command mode ? an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase ? an aligned group of four 16-bit words within the p-flash memory. each phrase includes two sets of aligned double words with each set including 7 ecc bits for single bit fault correction and double bit fault detection within each double word . p-flash memory ? the p-flash memory constitu tes the main nonvolatile memo ry store for applications. p-flash sector ? the p-flash sector is the smallest portion of the p- flash memory that can be erased. each p-flash sector contains 512 bytes. program ifr ? nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once field. 4.40.1.2 features 4.40.1.2.1 p-flash features ? single bit fault correction and double bit fault detect ion within a 32-bit double wo rd during read operations ? automated program and erase algorithm with verify and generation of ecc parity bits ? fast sector erase and phrase program operation ? ability to read the p-flash memory while programming a word in the d-flash memory ? flexible protection scheme to prevent accide ntal program or erase of p-flash memory 4.40.1.2.2 d-flash features ? single bit fault correction and double bit fault detection within a word during read operations
mm912_634 advance information, rev. 4.0 freescale semiconductor 295 ? automated program and erase algorithm with verify and generation of ecc parity bits ? fast sector erase and word program operation ? protection scheme to prevent accidental program or erase of d-flash memory ? ability to program up to four words in a burst sequence 4.40.1.2.3 other flash module features ? no external high-voltage power supply required for flash memory program and erase operations ? interrupt generation on flash command completion and flash error detection ? security mechanism to prevent unaut horized access to the flash memory 4.40.1.3 block diagram the block diagram of the flash module is shown in . 4.40.2 external signal description the flash module contains no signals that connect off-chip. 4.40.3 memory map and registers this section describes the memory map and registers for the fl ash module. read data from unimplemented memory space in the flash module is undefined. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. 4.40.3.1 module memory map the s12 architecture places the p-flash memory between global addresses .the p-flash memory map is shown in . the fprot register, described in section 4.40.3.2.9 , can be set to protect regions in the flash memory from accidental program or erase. the flash memory addresses cove red by these protectable regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code si nce it covers the vector space. default protection settings as well as security information that allows the m cu to restrict access to the flash module ar e stored in the flash configuration field as described in table 404 . table 404. flash configuration field global address size (bytes) description 0x3_ff00-0x3_ff07 8 backdoor comparison key refer to section 4.40.4.5.11, ?verify backdoor access key command ,? and section 4.40.5.1, ?unsecuring the mcu using backdoor key access ? 0x3_ff08-0x3_ff0b 4 reserved 0x3_ff0c 1 p-flash protection byte . refer to section 4.40.3.2.9, ?p-flash protection register (fprot)? 0x3_ff0d 1 d-flash protection byte . refer to section 4.40.3.2.10, ?d-flash protection register (dfprot)? 0x3_ff0e 1 flash nonvolatile byte refer to section 4.40.3.2.16, ?flash option register (fopt)? 0x3_ff0f 1 flash security byte refer to section 4.40.3.2.2, ?flash security register (fsec)? note: 201. 0x3ff08-0x3_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x3_ff08 - 0x3_ff0b reserved field should be programmed to 0xff.
mm912_634 advance information, rev. 4.0 freescale semiconductor 296 figure 113. d-flash and memory controller resource memory map table 405. program ifr fields global address size (bytes) field description 0x0_4000 ? 0x0_4007 8.0 reserved 0x0_4008 ? 0x0_40b5 174 reserved 0x0_40b6 ? 0x0_40b7 2.0 version id 0x0_40b8 ? 0x0_40bf 8.0 reserved 0x0_40c0 ? 0x0_40ff 64 program once field refer to section 4.40.4.5.6, ?program once command ? note: 202. for patch code storage, see section 4.40.4.2 203. used to track firmware patch versions, see section 4.40.4.2 table 406. d-flash and memory controller resource fields global address size (bytes) description 0x0_4000 ? 0x0_43ff 1,024 reserved 0x0_4400 ? 0x0_53ff 4,096 d-flash memory 0x0_5400 ? 0x0_57ff 1,024 reserved 0x0_5800 ? 0x0_5aff 768 memory cont roller scratch ram (ramon (204) = 1) 0x0_5b00 ? 0x0_5fff 1,280 reserved 0x0_6000 ? 0x0_67ff 2,048 reserved 0x0_6800 ? 0x0_7fff 6,144 reserved note: 204. mmcctl1 register bit d-flash memory 4 kbytes d-flash start = 0x0_4400 0x0_6000 d-flash end = 0x0_53ff p-flash ifr 1 kbyte 0x0_4000 reserved 1 kbyte scratch ram 768 bytes (ramon) ram end = 0x0_5aff ram start = 0x0_5800 reserved 6 kbytes reserved 2 kbytes reserved 1280 bytes 0x0_6800 0x0_7fff 0x0_40ff
mm912_634 advance information, rev. 4.0 freescale semiconductor 297 4.40.3.2 register descriptions the flash module contains a set of 20 control and status r egisters located between flash module base + 0x0000 and 0x0013. a summary of the flash module registers is given in figure 407 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and adversely affect memory controller behavior.
mm912_634 advance information, rev. 4.0 freescale semiconductor 298 4.40.3.2.1 flash clock di vider register (fclkdiv) the fclkdiv register is used to control ti med events in program and erase algorithms. table 407. ftmrc64k1 register summary address & name 76543210 fclkdiv rfdivld fdivlck fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w frsv0 r00000000 w fcnfg r ccie 00 ignsf 00 fdfd fsfd w fercnfg r000000 dfdie sfdie w fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w ferstat r000000 dfdif sfdif w dfprot r dpopen 000 dps3 dps2 dps1 dps0 w fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w frsv1 r00000000 w frsv2 r00000000 w frsv3 r00000000 w frsv4 r00000000 w fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w frsv5 r00000000 w frsv6 r00000000 w frsv7 r00000000 w = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 299 all bits in the fclkdiv register are readabl e, bit 7 is not writable, bit 6 is write- once-hi and controls the writability of th e fdiv field. caution the fclkdiv register must never be writte n to while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear. table 408. flash clock di vider regist er (fclkdiv) 76543210 rfdivld fdivlck fdiv[5:0] w reset00000000 = unimplemented or reserved table 409. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written since the last reset 1 fclkdiv register has been written since the last reset 6 fdivlck clock divider locked 0 fdiv field is open for writing 1 fdiv value is locked and cannot be changed. once the lock bi t is set high, only reset can clear this bit and restore writability to the fdiv field. 5?0 fdiv[5:0] clock divider bits ? fdiv[5:0] must be set to effectively divide busclk down to 1 mhz to control timed events during flash program and erase algorithms. table 410 shows recommended values for fdiv[5:0] based on the busclk frequency. please refer to section 4.40.4.3, ?flash command operations , ? for more information.
mm912_634 advance information, rev. 4.0 freescale semiconductor 300 4.40.3.2.2 flash securi ty register (fsec) the fsec register holds all bits associated wi th the security of the mcu and flash module. all bits in the fsec register are readable but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x3_ff0f located in p-flash memory (see table 404 ) as indicated by reset condition f in figure 411 . if a double bit fault is detected while reading the p-flash phrase containing the flash security byte during the reset sequence, a ll bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. table 410. fdiv values for various busclk frequencies busclk frequency (mhz) fdiv[5:0] busclk frequency (mhz) fdiv[5:0] min (205) max (206) min (205) max (206) 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 25.6 26.6 0x19 10.6 11.6 0x0a 26.6 27.6 0x1a 11.6 12.6 0x0b 27.6 28.6 0x1b 12.6 13.6 0x0c 28.6 29.6 0x1c 13.6 14.6 0x0d 29.6 30.6 0x1d 14.6 15.6 0x0e 30.6 31.6 0x1e 15.6 16.6 0x0f 31.6 32.6 0x1f note: 205. busclk is greater than this value. 206. busclk is less than or equal to this value. table 411. flash security register (fsec) 76543210 r keyen[1:0] rnv[5:2] sec[1:0] w resetffffffff = unimplemented or reserved table 412. fsec field descriptions field description 7?6 keyen[1:0] backdoor key security enable bits ? the keyen[1:0] bits define the enabling of backdoor key access to the flash module as shown in table 413 . 5?2 rnv[5:2} reserved nonvolatile bits ? the rnv bits should remain in the erased state for future enhancements. 1?0 sec[1:0] flash security bits ? the sec[1:0] bits define the security state of the mcu as shown in table 414 . if the flash module is unsecured using backdoor key access , the sec bits are forced to 10.
mm912_634 advance information, rev. 4.0 freescale semiconductor 301 the security function in the flash module is described in section 4.40.5 . 4.40.3.2.3 flash ccob in dex register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. 4.40.3.2.4 flash reserv ed0 register (frsv0) this flash register is re served for factory testing. all bits in the frsv0 register read 0 and are not writable. table 413. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled (207) 10 enabled 11 disabled note: 207. preferred keyen state to di sable backdoor key access. table 414. flash security states sec[1:0] status of security 00 secured 01 secured (208) 10 unsecured 11 secured note: 208. preferred sec state to set mcu to secured state table 415. fccob inde x register (fccobix) 76543210 r00000 ccobix[2:0] w reset00000000 = unimplemented or reserved table 416. fccobix field descriptions field description 2?0 ccobix[1:0] common command register index ? the ccobix bits are used to select which word of the fccob register array is being read or written to. see section 4.40.3.2.11, ?flash common command object register (fccob) ,? for more details. table 417. flash reserved0 register (frsv0) 76543210 r00000000 w reset00000000 = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 302 4.40.3.2.5 flash configur ation register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu. ccie, ignsf, fdfd, and fsfd bits are readable and writ able while remaining bits read 0 and are not writable. 4.40.3.2.6 flash error config uration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. all assigned bits in the fercnfg register are readable and writable. table 418. flash configuration register (fcnfg) 76543210 r ccie 00 ignsf 00 fdfd fsfd w reset00000000 = unimplemented or reserved table 419. fcnfg field descriptions field description 7 ccie command complete interrupt enable ? the ccie bit controls interrupt gener ation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the cci f flag in the fstat register is set (see section 4.40.3.2.7 ) 4 ignsf ignore single bit fault ? the ignsf controls single bit fault reporting in the ferstat register (see section 4.40.3.2.8 ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not repor ted and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect ? the fdfd bit allows the user to simula te a double bit fault during flash array read operations and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif flag in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the dfdi f flag in the ferstat register to be set (see section 4.40.3.2.7 ) and an interrupt will be generated as long as the dfdie interrupt enable in the fercnfg register is set (see section 4.40.3.2.6 ) 0 fsfd force single bit fault detect ? the fsfd bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual singl e bit fault is detected. 0 flash array read operations will set the sfdif flag in the ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdi f flag in the ferstat register to be set (see section 4.40.3.2.7 ) and an interrupt will be generated as long as the sfdie in terrupt enable in the fercnfg register is set (see section 4.40.3.2.6 ) table 420. flash error config uration register (fercnfg) 76543210 r000000 dfdie sfdie w reset00000000 = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 303 4.40.3.2.7 flash status register (fstat) the fstat register reports the operat ional status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mg busy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. table 421. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable ? the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif flag is set (see section 4.40.3.2.8 ) 0 sfdie single bit fault detect interrupt enable ? the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif flag is set (see section 4.40.3.2.8 ) 1 an interrupt will be requested w henever the sfdif flag is set (see section 4.40.3.2.8 ) table 422. flash status register (fstat) 76543210 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset1000000 (209) 0 (209) = unimplemented or reserved note: 209. reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 4.40.6 ). table 423. fstat field descriptions field description 7 ccif command complete interrupt flag ? the ccif flag indicates that a flash co mmand has completed. the ccif flag is cleared by writing a 1 to ccif to launch a command and ccif wi ll stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ? the accerr bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 4.40.4.3.2 ) or issuing an illegal flas h command. while accerr is set, the ccif flag cannot be cleared to launch a command. the accerr bit is cleared by writ ing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?the fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a comm and write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on f pviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ? the mgbusy flag reflects the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy executing a flash command (ccif = 0)
mm912_634 advance information, rev. 4.0 freescale semiconductor 304 4.40.3.2.8 flash error stat us register (ferstat) the ferstat register reflects the error status of internal flash operations. all flags in the ferstat register are r eadable and only writable to clear the flag. 4.40.3.2.9 p-flash protection register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that th e size of the protec ted region can only be increased. during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x3_f f0c located in p-flash memory (see table 404 ) as indicated by reset condition ?f? in . to change the p-flash protecti on that will be loaded during the reset sequence, th e upper sector of the p-flash memory must be unprotected, then the p-flas h protection byte must be reprogrammed. if a double bit fault is det ected while reading the p-flash phrase containing the p-flash prot ection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. 2 rsvd reserved bit ? this bit is reserved and always reads 0 . 1?0 mgstat[1:0] memory controller command completion status flag ? one or more mgstat flag bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 4.40.4.5, ?flash command description ,? and section 4.40.6, ?initialization ? for details. table 424. flash error status register (ferstat) 76543210 r000000 dfdif sfdif w reset00000000 = unimplemented or reserved table 425. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ? the setting of the dfdif flag indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. (210) the dfdif flag is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ? with the ignsf bit in the fcnfg regist er clear, the sfdif flag indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flas h command operation. the sfdif flag is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted note: 210. the single bit fault and double bit fault fl ags are mutually exclusive for parity errors (an ecc fault occurrence can be ei ther single fault or double fault but never both). a simultaneous access collisi on (read attempted while command running) is indicated when both sfdif and dfdif flags are high. table 423. fstat field descriptions (continued) field description
mm912_634 advance information, rev. 4.0 freescale semiconductor 305 although the protection scheme is loaded fr om the flash memory at global address 0x3_ff0c during the reset sequence, it can be changed by the user. the p-flash protec tion scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. 4.40.3.2.10 d-flas h protection register (dfprot) the dfprot register defines which d-flash sectors are protected against progr am and erase operations. the (unreserved) bits of the dfprot regi ster are writable with the rest riction that protection can be added but not removed. writes must increase the dps value and the dpopen bit can onl y be written from 1 (protection disabled) to 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x3_ff0d located in p-flash memory (see table 404 ) as indicated by reset condition f in figure 428 . to change the d-flash protec tion that will be loaded during the reset seq uence, the p-flash sector containing the d-flash protection byte must be unprotect ed, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the p-flas h phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. block erase of the d-flash memory is not possible if any of t he d-flash sectors are protected. table 426. fprot field descriptions field description 6 rnv[6] reserved nonvolatile bit ? the rnv bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ? the fphdis bit determines whether there is a protected/unprotected area in a specific region of the p-flas h memory ending with global address 0x3_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4?3 fphs[1:0] flash protection higher address size ? the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in table 427 . the fphs bits can only be writt en to while the fphdis bit is set. table 427. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x3_f800?0x3_ffff 2.0 kbyte 01 0x3_f000?0x3_ffff 4.0 kbyte 10 0x3_e000?0x3_ffff 8.0 kbyte 11 0x3_c000?0x3_ffff 16 kbyte table 428. d-flash protection register (dfprot) 76543210 r dpopen 000 dps[3:0] w reset f 0 0 0 f f f f = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 306 4.40.3.2.11 flash comm on command object register (fccob) the fccob is an array of six words addressed via the ccobix in dex found in the fccobix regist er. byte wide reads and writes are allowed to the fccob register. 4.40.3.2.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command?s execution by writing a 1 to the c cif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif table 429. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and er ase with protected address range defined by dps bits 1 disables d-flash memory prot ection from program and erase 3?0 dps[3:0] d-flash protection size ? the dps[3:0] bits determine the size of the protected area in the d-flash memory as shown in ta b l e 4 3 0 . table 430. d-flash protection address range dps[3:0] global address range protected size 0000 0x0_4400 ? 0x0_44ff 256 bytes 0001 0x0_4400 ? 0x0_45ff 512 bytes 0010 0x0_4400 ? 0x0_46ff 768 bytes 0011 0x0_4400 ? 0x0_47ff 1024 bytes 0100 0x0_4400 ? 0x0_48ff 1280 bytes 0101 0x0_4400 ? 0x0_49ff 1536 bytes 0110 0x0_4400 ? 0x0_4aff 1792 bytes 0111 0x0_4400 ? 0x0_4bff 2048 bytes 1000 0x0_4400 ? 0x0_4cff 2304 bytes 1001 0x0_4400 ? 0x0_4dff 2560 bytes 1010 0x0_4400 ? 0x0_4eff 2816 bytes 1011 0x0_4400 ? 0x0_4fff 3072 bytes 1100 0x0_4400 ? 0x0_50ff 3328 bytes 1101 0x0_4400 ? 0x0_51ff 3584 bytes 1110 0x0_4400 ? 0x0_52ff 3840 bytes 1111 0x0_4400 ? 0x0_53ff 4096 bytes table 431. flash common command object high register (fccobhi) 76543210 r ccob[15:8] w reset00000000 table 432. flash common command object low register (fccoblo) 76543210 r ccob[7:0] w reset00000000
mm912_634 advance information, rev. 4.0 freescale semiconductor 307 bit in the fstat register all fccob parameter fields are locke d and cannot be changed by the user until the command completes (as evidenced by the memory controller returning ccif to 1). so me commands return informati on to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 433 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111 ) are ignored with reads from these fields returning 0x0000. table 433 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 4.40.4.5 . 4.40.3.2.12 flash reserv ed1 register (frsv1) this flash register is re served for factory testing. all bits in the frsv1 register read 0 and are not writable. 4.40.3.2.13 flash reserv ed2 register (frsv2) this flash register is re served for factory testing. all bits in the frsv2 register read 0 and are not writable. 4.40.3.2.14 flash reserv ed3 register (frsv3) this flash register is re served for factory testing. table 433. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] defining flash command lo 6?h0, global address [17:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0] 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] table 434. flash reserved1 register (frsv1) 76543210 r00000000 w reset00000000 = unimplemented or reserved table 435. flash reserved2 register (frsv2) 76543210 r00000000 w reset00000000 = unimplemented or reserved
mm912_634 advance information, rev. 4.0 freescale semiconductor 308 all bits in the frsv3 register read 0 and are not writable. 4.40.3.2.15 flash reserv ed4 register (frsv4) this flash register is re served for factory testing. all bits in the frsv4 register read 0 and are not writable. 4.40.3.2.16 flash opti on register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. during the reset sequence, the fopt register is loaded from t he flash nonvolatile byte in the flash configuration field at glob al address 0x3_ff0e located in p-flash memory (see table 404 ) as indicated by reset condition f in figure 438 . if a double bit fault is detected while reading the p-flash phrase containing th e flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. 4.40.3.2.17 flash reserv ed5 register (frsv5) this flash register is re served for factory testing. table 436. flash reserved3 register (frsv3) 76543210 r00000000 w reset00000000 = unimplemented or reserved table 437. flash reserved4 register (frsv4) 76543210 r00000000 w reset00000000 = unimplemented or reserved table 438. flash option register (fopt) 76543210 r nv[7:0] w resetffffffff = unimplemented or reserved table 439. fopt field descriptions field description 7?0 nv[7:0] nonvolatile bits ? the nv[7:0] bits are available as nonvolatile bits. refer to the devic e user guide for proper use of the nv bits. table 440. flash reserved5 register (frsv5) 76543210 r00000000 w
mm912_634 advance information, rev. 4.0 freescale semiconductor 309 all bits in the frsv5 register read 0 and are not writable. 4.40.3.2.18 flash reserv ed6 register (frsv6) this flash register is re served for factory testing. all bits in the frsv6 register read 0 and are not writable. 4.40.3.2.19 flash reserv ed7 register (frsv7) this flash register is re served for factory testing. all bits in the frsv7 register read 0 and are not writable. 4.40.4 functional description 4.40.4.1 modes of operation the ftmrc64k1 module provides th e modes of operation shown in table 443 . the operating mode is determined by module-level inputs and affects the fclkdiv, fcnfg, and df prot registers, scratch ram writes, and the command set availability (see table 445 ). 4.40.4.2 ifr version id word the version id word is stored in the ifr at addre ss 0x0_40b6. the contents of the word are defined in table 444 . vernum: version number. the first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ?none?. reset00000000 = unimplemented or reserved table 441. flash reserved6 register (frsv6) 76543210 r00000000 w reset00000000 = unimplemented or reserved table 442. flash reserved7 register (frsv7) 76543210 r00000000 w reset00000000 = unimplemented or reserved table 443. modes and mode control inputs operating mode ftmrc input mmc_mode_ss_t2 normal: 0 special: 1 table 444. ifr version id fields [15:4] [3:0] reserved vernum table 440. flash reserved5 register (frsv5)
mm912_634 advance information, rev. 4.0 freescale semiconductor 310 4.40.4.3 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: ? how to write the fclkdiv register that is used to generate a time base (fclk) derived from busclk for flash program and erase command operations ? the command write sequence used to set fl ash command parameters and launch execution ? valid flash commands available for execution 4.40.4.3.1 writing the fclkdiv register prior to issuing any flash program or erase command after a rese t, the user is required to write the fclkdiv register to divide busclk down to a target fclk of 1 mhz. table 410 shows recommended values for the fdiv field based on busclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 0.8 mhz. setting fdiv too high can destr oy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasur e of the flash memory cells. when the fclkdiv register is wr itten, the fdivld bit is set aut omatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if th e fclkdiv register has not been written, any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fs tat register will set. 4.40.4.3.2 command write sequence the memory controller will launch all valid flas h commands entered usi ng a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 4.40.3.2.7 ) and the ccif flag should be tested to determine the status of the current command write sequence. if ccif is 0, the previous command write sequence is still active, a new command write sequence cannot be starte d, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. 4.40.4.3.2.1 defin e fccob contents the fccob parameter fields must be loaded with all required para meters for the flash command being executed. access to the fccob parameter fields is controlled via t he ccobix bits in the fccobix register (see section 4.40.3.2.3 ). the contents of the fccob parameter fields are transferred to the memory controller when the user clears the ccif command completion flag in the fstat register (wri ting 1 clears the ccif to 0). the ccif flag will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the flow for a gen eric command write s equence is shown in figure 114 .
mm912_634 advance information, rev. 4.0 freescale semiconductor 311 figure 114. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register start check fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no fdiv correct? no bit polling for command completion check yes ccif set? to identify specific command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset read: fstat register no yes ccif set? no yes ccif set? clock divider value check read: fstat register
mm912_634 advance information, rev. 4.0 freescale semiconductor 312 4.40.4.3.3 valid flash module commands 4.40.4.3.4 p-flash commands table 446 summarizes the valid p-flash commands along with the ef fects of the commands on the p-flash block and other resources within the flash module. table 445. flash commands by mode fcmd command unsecured secured ns (211) ss (212) ns (213) ss (214) 0x01 erase verify all blocks ???? 0x02 erase verify block ???? 0x03 erase verify p-flash section ??? 0x04 read once ??? 0x06 program p-flash ??? 0x07 program once ??? 0x08 erase all blocks ?? 0x09 erase flash block ??? 0x0a erase p-flash sector ??? 0x0b unsecure flash ?? 0x0c verify backdoor access key ?? 0x0d set user margin level ??? 0x0e set field margin level ? 0x10 erase verify d-flash section ??? 0x11 program d-flash ??? 0x12 erase d-flash sector ??? note: 211. unsecured normal single chip mode 212. unsecured special single chip mode 213. secured normal single chip mode 214. secured special single chip mode table 446. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that al l p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify t hat a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words star ting at the address provided are erased. 0x04 read once read a dedicated 64 byte field in the nonvolatile in formation register in p-flash block that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64 byte field in the nonvolatile information register in p-flash block that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash (and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possi ble when fpldis, fphdis and fpopen bits in the fprot register are set prio r to launching the command. 0x0a erase p-flash sector erase al l bytes in a p-flash sector.
mm912_634 advance information, rev. 4.0 freescale semiconductor 313 4.40.4.3.5 d-flash commands table 447 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. 4.40.4.4 allowed simultaneous p-flash and d-flash operations only the operations marked ?ok? in table 448 are permitted to be run simultaneously on the program flash and data flash blocks. some operations cannot be executed simultaneously bec ause certain hardware resources are shared by the two memories. the priority has been placed on permitting program fl ash reads while program and erase operations execute on the data flash, providing read (p-flash) while write (d-flash) functionality. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash ( and d-flash) blocks and verifying that all p-flash (and d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level specifies a user margin read level for all p-flash blocks. 0x0e set field margin level specifies a field margin read level for all p-flash blocks (special modes only). table 447. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that al l d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify t hat the d-flash block is erased. 0x08 erase all blocks erase all d-flash ( and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (or p-flash) block. an erase of the full d-flash blo ck is only possible when dpopen bit in the dfprot register is set prior to launching the command. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash ( and p-flash) blocks are erased. 0x0d set user margin level specifies a user margin read level for the d-flash block. 0x0e set field margin level specifies a field margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words star ting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector er ase all bytes in a sector of the d-flash block. table 448. allowed p-flash and d-flash simultaneous operations data flash program flash read margin read (215) program sector erase mass erase (217) read ok ok ok margin read (215) ok (216) program sector erase ok table 446. p-flash commands fcmd command function on p-flash memory
mm912_634 advance information, rev. 4.0 freescale semiconductor 314 4.40.4.5 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the comm and write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: ? starting any command write sequence that programs or eras es flash memory before initializing the fclkdiv register ? writing an invalid command as part of the command write sequence ? for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the r ead operation will return invalid data. if the sfdif or dfdif flags were not prev iously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set. if the accerr or fpviol bits are set in the fstat register, th e user must clear these bits bef ore starting any command write sequence (see section 4.40.3.2.7 ). caution a flash word or phrase must be in the eras ed state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 4.40.4.5.1 erase verify all blocks command the erase verify all blocks command will verify t hat all p-flash and d-flash blocks have been erased. upon clearing ccif to launch the erase verify all blocks comm and, the memory controller will verify that the entire flash memory space is erased. the ccif flag will set afte r the erase verify all bl ocks operation has completed. 4.40.4.5.2 erase verify block command the erase verify block command allows the user to verify t hat an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be verified. mass erase (215) ok note: 215. a ?margin read? is any read after ex ecuting the margin setting commands ?set user margin level? or ?set field margin level? with anything but the ?normal? level specified. 216. see the note on margin settings in section 4.40.4.5.12 and section 4.40.4.5.13 . 217. the ?mass erase? operations are commands ?e rase all blocks? and ?erase flash block?. table 449. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 450. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable e rrors have been encountered during the read table 448. allowed p-flash and d-flash simultaneous operations data flash program flash read margin read (215) program sector erase mass erase (217)
mm912_634 advance information, rev. 4.0 freescale semiconductor 315 upon clearing ccif to launch the erase veri fy block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif flag will set afte r the erase verify block operation has completed. 4.40.4.5.3 erase verify p-flash section command the erase verify p-flash section command will verify that a section of code in the p- flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. upon clearing ccif to launch the erase verify p-flash section co mmand, the memory controller will verify the selected section of flash memory is erased. the ccif flag will set after the erase verify p- flash section operation has completed. 4.40.4.5.4 read once command the read once command provides read access to a reserved 64 by te field (8 phrases) located in the nonvolatile information register of p-flash. the read once field is progra mmed using the program once command described in section 4.40.4.5.6 . the read once command must not be executed from the flash blo ck containing the program once reserved field to avoid code runaway. table 451. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [17:16] of the flash block to be verified . table 452. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if an invalid global address [17:16] is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable e rrors have been encountered during the read table 453. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [17:16] of a p-flash block 001 global address [15:0] of the first phrase to be verified 010 number of phrases to be verified table 454. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) set if the requested section crosses a 128 kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable e rrors have been encountered during the read
mm912_634 advance information, rev. 4.0 freescale semiconductor 316 upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif flag will set after the read once operati on has completed. valid phrase index values for the read once command range from 0x0000 to 0x0007. duri ng execution of the read on ce command, any attempt to read addresses within p-flash block will return invalid data. 8 4.40.4.5.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. upon clearing ccif to launch the program p- flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif flag will set after the program p-flash operation has completed. table 455. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value table 456. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 445 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable e rrors have been encountered during the read table 457. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [17:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed (218) 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value note: 218. global address [2:0] must be 000
mm912_634 advance information, rev. 4.0 freescale semiconductor 317 4.40.4.5.6 program once command the program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in p-flash. the program once reserved field can be read using the read once command as described in section 4.40.4.5.4 . the program once command must only be issued once since the nonvolatile information register in p-flash cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memo ry controller first verifies that the selected phrase is erased. if erased, then the selected phrase will be programmed and then verified with read back. the ccif flag will remain clea r, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash will return invalid data. 4.40.4.5.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. table 458. program p-flas h command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the global address [17:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 459. program once co mmand fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value table 460. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 445 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed (219) fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation note: 219. if a program once phrase is initially programmed to 0xfff f_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase.
mm912_634 advance information, rev. 4.0 freescale semiconductor 318 upon clearing ccif to la unch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memo ry controller verifies that the entire flas h memory space was properly erased, securit y will be released. during the execution of th is command (ccif=0) the user must not write to any flash module register. the ccif flag will set after the erase all blocks operation has completed. 4.40.4.5.8 erase flash block command the erase flash block operation will erase a ll addresses in a p-flash or d-flash block. upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif flag will set after the erase flash block operation has completed. 4.40.4.5.9 erase p-flash sector command the erase p-flash sector operation will er ase all addresses in a p-flash sector. table 461. erase all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 462. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 445 ) fpviol set if any area of the p-flas h or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 463. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [17:16] to identify flash block 001 global address [15:0] in flash block to be erased table 464. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:16] is supplied set if the supplied p-flash address is not phr ase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 465. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [17:16] to identify p-flash block to be erased 001 global address [15:0] anywhere with in the sector to be erased. refer to section 4.40.1.2.1 for the p-flash sector size.
mm912_634 advance information, rev. 4.0 freescale semiconductor 319 upon clearing ccif to launch the erase p-flash sector command, the memory controller will eras e the selected flash sector and then verify that it is erased. the ccif flag will be set after the erase p-flash sector operation has completed. 4.40.4.5.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory contro ller verifies that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execut ion of this command (ccif=0) the user must not write to any flash module register. the ccif flag is set after the unsecure flash operation has completed. 4.40.4.5.11 verify backdo or access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 413 ). the verify backdoor access key comm and releases security if user-suppli ed keys match those stored in the flash security bytes of the flash configuration field (see table 404 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access ke y command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, th e memory controller sets the acce rr bit in the fstat register an d table 466. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:16] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the selected p- flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 467. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required table 468. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 445 ) fpviol set if any area of the p-flas h or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 469. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3
mm912_634 advance information, rev. 4.0 freescale semiconductor 320 terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash configuration field with key 0 compared to 0x3_ ff00, etc. if the backdoor keys ma tch, security will be release d. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a re set occurs. the ccif flag is set after the verify backdoor access key operation has completed. 4.40.4.5.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of the p-flash or d-flash block. upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif flag. note when the d-flash block is target ed, the d-flash user margin levels are applied only to the d-flash reads. however, when the p-flash block is targeted, the p-flas h user margin levels are applied to both p-flash and d-flash reads. it is not possible to apply user margin levels to the p-flash block only. valid margin level settings for the set user margin level command are defined in ta b l e 4 7 2 . table 470. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0] != 10, see section 4.40.3.2.2 ) set if the backdoor key has mi smatched since the last reset fpviol none mgstat1 none mgstat0 none table 471. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [17:16] to identify the flash block 001 margin level setting table 472. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level (220) 0x0002 user margin-0 level (221) note: 220. read margin to the erased state 221. read margin to the programmed state
mm912_634 advance information, rev. 4.0 freescale semiconductor 321 note user margin levels can be used to check that flash memory cont ents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin leve ls, a potential loss of information has been detected. 4.40.4.5.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of the p-flash or d-flash block. upon clearing ccif to launch the set field margin level comma nd, the memory controller will se t the field margin level for the targeted block and then set the ccif flag. note when the d-flash block is targeted, the d-flash field margin levels are applied only to the d-flash reads. however, when the p-flash block is targeted, the p-flash field margin levels are applied to both p-flash and d-flash reads. it is not possible to apply field margin levels to the p-flash block only. valid margin level settings for the set field margin level command are defined in table 475 . table 473. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none table 474. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [17:16] to identify the flash block 001 margin level setting table 475. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level (222) 0x0002 user margin-0 level (223) 0x0003 field margin-1 level (222) 0x0004 field margin-0 level (223) note: 222. read margin to the erased state 223. read margin to the programmed state
mm912_634 advance information, rev. 4.0 freescale semiconductor 322 caution field margin levels must only be used during verify of the initial factory programming . note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level settin g. if unexpected results are encountered when checking flash memory contents at field marg in levels, the flash memory contents should be erased and reprogrammed. 4.40.4.5.14 erase verify d-flash section command the erase verify d-flash section command will verify that a sect ion of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. upon clearing ccif to launch the erase verify d-flash section command, the memory c ontroller will verify the selected section of d-flash memory is erased. the ccif flag will set after the erase verify d-flash sect ion operation has completed. 4.40.4.5.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. table 476. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none table 477. erase verify d-flash s ection command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [17:16] to identify the d-flash block 001 global address [15:0] of the first word to be verified 010 number of words to be verified table 478. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable e rrors have been encountered during the read
mm912_634 advance information, rev. 4.0 freescale semiconductor 323 upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif flag is set when the operation has completed. 4.40.4.5.16 erase d-fl ash sector command the erase d-flash sector operat ion will erase all addresses in a sector of the d-flash block. upon clearing ccif to launch the erase d-fl ash sector command, the memory controll er will erase the selected flash sector and verify that it is erased. the ccif flag will set af ter the erase d-flash sector operation has completed. table 479. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [17:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired 101 word 3 program value, if desired table 480. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 481. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [17:16] to identify d-flash block 001 global address [15:0] anywhere with in the sector to be erased. see section 4.40.1.2.2 for d-flash sector size. table 482. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 445 ) set if an invalid global address [17:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
mm912_634 advance information, rev. 4.0 freescale semiconductor 324 4.40.4.6 interrupts the flash module can generate an interrupt when a flash command operation has completed or when a flash command operation has detected an ecc fault. note vector addresses and their relative interrupt priority are determined at the mcu level. 4.40.4.6.1 description of flash interrupt operation the flash module uses the ccif flag in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif flags in combination with the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed de scription of the register bits involved, refer to section 4.40.3.2.5, ?flash configurati on register (fcnfg) ?, section 4.40.3.2.6, ?flash error configuration register (fercnfg) ?, section 4.40.3.2.7, ?flash status register (fstat) ?, and section 4.40.3.2.8, ?flash erro r status register (ferstat) ?. the logic used for generating the flash module interrupts is shown in figure 115 . figure 115. flash module interrupts implementation 4.40.4.7 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash op eration will be completed before the cpu is allowed to enter stop mode. 4.40.5 security the flash module provides security informati on to the mcu. the flash security state is defined by the sec bits of the fsec register (see table 414 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash configuration field at global address 0x3_ff0f. the security state out of reset can be permanently changed by programming the security byte assuming t hat the mcu is starting from a mode wher e the necessary p-flash erase and program commands are available and that the upper region of the p-flash is unprotected. if the flash se curity byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: ? unsecuring the mcu using backdoor key access ? unsecuring the mcu in special single chip mode using bdm ? mode and security effects on flash command availability table 483. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
mm912_634 advance information, rev. 4.0 freescale semiconductor 325 4.40.5.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access featur e which requires knowledge of the contents of the backdoor keys (four 16-bit words progra mmed at addresses 0x3_ff00-0x3_ff0 7). if the keyen[1:0] bits are in the enabled state (see section 4.40.3.2.2 ), the verify backdoor access key command (see section 4.40.4.5.11 ) allows the user to present four prospective keys for comparison to the keys stored in the flash me mory via the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memo ry, the sec bits in the fsec register (see table 414 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not pe rmitted as backdoor keys. while the verify backdoor access key command is active, p-flash memory and d-flash memory will not be available for read access and will return invalid data. the user code stored in the p- flash memory must have a method of receiving t he backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bi ts are in the ena bled state (see section 4.40.3.2.2 ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 4.40.4.5.11 2. if the verify backdoor access key comm and is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the me mory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the on ly method to re-enable the verify backdoor access key command. the security as defined in the flash security byte (0x3_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x3_ff00-0x3_ff07 are unaffected by the verify backdoor access key command sequence. the verify backdoor access key command sequence has no effect on the program and erase protections defined in the flas h protection register, fprot. after the backdoor keys have been correctly matched, the m cu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_ff00-0x3_ff07 in the fl ash configuration field. 4.40.5.2 unsecuring the mcu in sp ecial single chip mode using bdm a secured mcu can be unsecured in special single chip mode by using the following method to erase the p-flash and d-flash memory: 1. reset the mcu into special single chip mode 2. delay while the bdm executes the erase verify all blocks command write sequence to check if the p-flash and d-flash memories are erased 3. send bdm commands to disable protec tion in the p-flash and d-flash memory 4. execute the erase all blocks command write sequence to erase the p-flash and d-flash memory 5. after the ccif flag sets to indicate th at the erase all blocks operation has comple ted, reset the mcu in to special single chip mode 6. delay while the bdm executes the erase verify all blo cks command write sequence to verify that the p-flash and d-flash memory are erased if the p-flash and d-flash memory are verified as erased, t he mcu will be unsecured. all bdm commands will now be enabled and the flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. send bdm commands to execute the program p-flash command write sequence to program the flash security byte to the unsecured state 8. reset the mcu 4.40.5.3 mode and security effects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in table 445 . 4.40.6 init ialization on each system reset the flash module executes a reset s equence which establishes initial values for the flash block configuration parameters, the fprot and df prot protection registers, and the fopt and fsec registers. the flash module reverts to using built-in default values that leave the module in a fully protected and secured st ate if errors are encountered during
mm912_634 advance information, rev. 4.0 freescale semiconductor 326 execution of the reset sequence. if a double bit fault is detect ed during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset se quence. the flash module holds off all cpu access for the initial portion of the rese t sequence. while flash memory reads and access to most flash regi sters are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored. comple tion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fc coblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
mm912_634 advance information, rev. 4.0 freescale semiconductor 327 4.41 die-to-die initiator (d2div1) 4.41.0.1 preface this document contains the user specification of the d2d initiator. 4.41.0.1.1 acronyms and abbreviations table 484 contains sample acronyms and abbr eviations used in this document. 4.41.0.1.2 glossary table 485 shows a glossary of the major terms used in this document. 4.41.1 introduction this section describes the functi onality of the die-to-die (d2div1) initiator block especially designed for low cost connection s between a microcontroller die (interface initiator) and an anal og die (interface target) located in the same package. the d2di block ? realizes the initiator part of the d2d interface, including supervision and error interrupt generation ? generates the clock for this interface ? disables/enables the interrupt from the d2d interface 4.41.1.1 overview the d2di is the initiator for a data transfer to and from a ta rget typically located on another die in the same package. it pro vides a set of configuration registers and two memory mapped 256 byte address windows. wh en writing to a window a transaction is initiated sending a write command, followed by an 8-bit address and the data byte or word to the target. when reading from a window a transaction is initiated sending a read command, followed by an 8-bit address to the tar get. the target then responds with the data. the basic idea is that a peripheral located on anot her die, can be addressed like an on-chip peripheral, except for a small transaction delay. table 484. acronyms and abbreviated terms term meaning d2d die-to-die table 485. glossary term definition active low the signal is asserted when it changes to logic-level zero. active high the signal is asserted when it changes to logic-level one. asserted discrete signal is in active logic state. customer the end user of an soc design or device. eot end of transaction negated a discrete signal is in inactive logic state. pin external physical connection. revision revised or new version of a document. revi sions produce versions; th ere can be no ?rev 0.0.? signal electronic construct whose state or change in state conveys information. transfer a read or write on the cpu bus following the ip-bus protocol. transaction command, address and if required data sent on the d2d interface. a transaction is fini shed by the eot acknowledge cy cle. version particular form or variation of an earlier or original document.
mm912_634 advance information, rev. 4.0 freescale semiconductor 328 figure 116. die-to-die init iator (d2di) block diagram 4.41.1.2 features the main features of this block are ? software transparent, memory mapped access to peripherals on target die ? 256 byte address window ? supports blocking read or write as we ll as non-blocking write transactions ? scalable interface clock divide by 1, 2, 3, or 4 of bus clock ? clock halt on system stop ? configurable for 4 or 8-bit wide transfers ? configurable timeout period ? non-maskable interrupt on transaction errors ? transaction status and error flags ? interrupt enable for receiving interrupt (from d2d target) 4.41.1.3 modes of operation 4.41.1.3.1 d2di in stop mode the d2di stops working in stop mode. the d2dclk signal as we ll as the data signals used are driven low (only after the end of the current high phase, as defined by d2dclkdiv). waking from stop mode, the d2dclk line starts clocking again an d the data lines will be driven low until the first transaction starts. stop mode is entered by different cpu instructions. every (enabled) interrupt can be used to leave the stop mode. d2dclk d2ddat[7:0] /n n=1 ? 4 bus clock d2dint d2dcw address and data buffer d2die address bus write data bus read data bus d2dinti d2derr_int xfr_wait d2dif d2dclkdiv
mm912_634 advance information, rev. 4.0 freescale semiconductor 329 4.41.1.3.2 d2di in special modes the mcu can enter a special mode (used for test and debugging pu rposes as well as programming the flash). in the d2di the ?write-once? feature is disabled. see the mcu description for details. 4.41.2 external signal description the d2di optionally uses 6 or 10 port pins. the functions of t hose pins depends on the settings in the d2dctl0 register, when the d2di module is enabled. 4.41.2.1 d2dclk when the d2di is enabled this pin is the clock output. this signal is low if the initiator is disabled, in stop mode (with d2ds wai asserted), otherwise it is a continuos clock. this pin may be shared with general purpose function ality if the d2di is disabled . 4.41.2.2 d2ddat[7:4] when the d2di is enabled and the interface connection width d2dcw is set to be 8-bit wide, those lines carry the data bits 7:4 acting as outputs or inputs. when they act as inputs pull-down elements are enabled. if the d2di is disabled or if the interfac e connection width is set as 4-bit wide, the pins may be shared with general purpose pin functionality. 4.41.2.3 d2ddat[3:0] when the d2di is enabled those lines carry the data bits 3:0 acting as outputs or inputs. when they act as inputs pull-down elements are enabled. if the d2di is disabled the pins and may be shared with general purpose pin functionality. 4.41.2.4 d2dint the d2dint is an active input interrupt input driven by the ta rget device. the pin has an active pull-down device. if the d2di is disabled the pin may be shared wit h general purpose pin functionality. see the port interface module (pim) guid e for details of the gpio function. 4.41.3 memory map and register definition 4.41.3.1 memory map the d2di memory map is split into three sections. 1. an eight-byte set of control registers 2. a 256 byte window for blocking transactions 3. a 256 byte window for non-blocking transactions see the chapter ?device memory map? for the regi ster layout (distribut ion of these sections). table 486. signal properties name primary (d2den=1) i/o secondary (d2den=0) reset comment pull down d2ddat[7:0] bi-directional data lines i/o gpio 0 driven low if in stop mode active (224) d2dclk interface clock signal o gpio 0 low if in stop mode ? d2dint active high interrupt i gpio ? ? active (225) note: 224. active if in input state, only if d2den=1 225. only if d2den=1
mm912_634 advance information, rev. 4.0 freescale semiconductor 330 figure 117. d2di top level memory map a summary of the registers associated with the d2di block is shown in figure 487 . detailed descriptions of the registers and bits are given in the subsections that follow. 4.41.3.2 register definition 4.41.3.3 d2di control register 0 (d2dctl0) this register is used to enable and configure the interface wid th, the wait behavior and the frequency of the interface clock. table 487. d2di register summary offset register name bit 7654321bit 0 0x0 d2dctl0 r d2den d2dcw d2dswai 000 d2dclkdiv[1:0] w 0x1 d2dctl1 d2die 000 timeout[3:0] 0x2 d2dstat0 r errif ackerf cnclf timef terrf parf par1 par0 w 0x3 d2dstat1 d2dif d2dbsy 0 00000 0x4 d2dadrhi r rwb sz8 0 nblk0000 w 0x5 d2dadrlo r adr[7:0] w 0x6 d2ddatahi r data[15:8] w 0x7 d2ddatalo r data[7:0] w = unimplemented or reserved table 488. d2di control register 0 (d2dctl0) offset 0x0 access: user read/write 76543210 r d2den d2dcw d2dswai 000 d2dclkdiv[1:0] w reset00000000 8 byte control registers 256 byte window blocking access 256 byte window non-blocking write d2dregs d2dblk d2dnblk
mm912_634 advance information, rev. 4.0 freescale semiconductor 331 the clock divider will provide the waveforms as shown in figure 118 . the duty cycle of the clock is not always 50%, the high cycle is shorter than 50% or equal but never longer, since this is beneficial for the transaction speed. figure 118. interface clock wavefo rms for various d2dclkdiv encoding 4.41.3.4 d2di control register 1 (d2dctl1) this register is used to enable the d2 di interrupt and set number of d2dclk cycl es before a timeout error is asserted. table 489. d2dctl0 register field descriptions field description 7 d2den d2di enable ? enables the d2di module. this bit is write-once in normal mode and can always be written in special modes. 0 d2di initiator is disabled. no lines are not us ed, the pins have their gp io (secondary) function. 1 d2di initiator is enabled. after setting d2den=1 the d2 ddat[7:0] (or [3:0], see d2dcw) lines are driven low with the idle command; the d2dclk is driven by the divided bus clock. 6 d2dcw d2d connection width ? sets the number of data lines used by the interf ace. this bit is write-once in normal modes and can always be written in special modes. 0 lines d2ddat[3:0] are used for four line data transfer. d2ddat[7:4] are unused. 1 all eight interface lines d2ddat[7:0] are used for data transfer. 5 - reserved ? for internal use 4:2 reserved, should be written to 0 to ensure compat ibility with future versions of this interface. 1:0 d2dclkdiv interface clock divider ? determines the frequency of the interface cloc k. these bits are write-once in normal modes and can be always written in special modes. see figure 118 for details on the clock waveforms 00 encoding 0. bus clock divide by 1. 01 encoding 1. bus clock divide by 2. 10 encoding 2. bus clock divide by 3. 11 encoding 3. bus clock divide by 4. table 490. d2di control register 1 (d2dctl1) offset 0x1 access: user read/write 76543210 r d2die 0 0 0 timout[3:0] w reset00000000 table 491. d2dctl1 register field descriptions field description 7 d2die d2d interrupt enable ? enables the external interrupt 0 external interrupt is disabled 1 external interrupt is enabled 00 01 10 11 bus clock
mm912_634 advance information, rev. 4.0 freescale semiconductor 332 note ?write-once? means that after writing d2dcnt l0.d2den=1 the write accesses to these bits have no effect. 4.41.3.5 d2di status register 0 (d2dstat0) this register reflects the st atus of the d2di transactions. 4.41.3.6 d2di status register 1 (d2dstat1) this register holds the status of th e external interrupt pin and an indica tor about the d2di transaction status. 6:4 reserved, should be written to 0 to ensure compat ibility with future versions of this interface. 3:0 timout timeout setting ? defines the number of d2dclk cycles to wait after the last transaction cycle until a timeout is asserted. in case of a timeout the timef flag in the d2dstat0 register will be set. these bits are write-once in normal modes and can always be written in special modes. 0000: the acknowledge is expected directly after the last transfer, i.e. the target must not insert a wait cycle. 0001 - 1111: the target may insert up to timout wait states before acknowledging a transacti on until a timeout is asserted table 492. d2di status register 0 (d2dstat0) offset 0x2 access: user read/write 76543210 r errif ackerf cnclf timef terrf parf par1 par0 w reset00000000 table 493. d2di status regi ster 0 field descriptions field description 7 errif d2di error interrupt flag ? this status bit indicates that the d2d initia tor has detected an error c ondition (summary of the following five flags).this interrupt is not locally maskable. write a 1 to clear the flag. writing a 0 has no effect. 0 d2di has not detected an error during a transaction. 1 d2di has detected an error during a transaction. 6 ackerf acknowledge error flag ? this read-only flag indicates that in the ack nowledge cycle not all data inputs are sampled high, indicating a potential broken wire. this flag is cleared when t he errif bit is cleared by writing a 1 to the errif bit. 5 cnclf cnclf ? this read-only flag indicates the initiator has canceled a transaction and replaced it by an idle command due to a pending error flag (errif). this flag is cleared when the e rrif bit is cleared by writing a 1 to the errif bit. 4 timef time out error flag ? this read-only flag indicates the initiator has detected a time-out error. this flag is cleared when the errif bit is cleared by writing a 1 to the errif bit. 3 terrf transaction error flag ? this read-only flag indicates the initiator has det ected the error signal during the acknowledge cycle of the transaction. this flag is cleared when the errif bit is cleared by writing a 1 to the errif bit. 2 parf parity error flag ? this read-only flag indicates the initiator has detected a pa rity error. parity bits[1:0] contain further information. this flag is cleared when the errif bit is cleared by writing a 1 to the errif bit. 1 par1 parity bit ? p[1] as received by the d2di 0 par0 parity bit ? p[0] as received by the d2di table 491. d2dctl1 register field descriptions field description
mm912_634 advance information, rev. 4.0 freescale semiconductor 333 4.41.3.7 d2di address bu ffer register (d2dadr) this read-only register contains information about the ongoing d2d interface transaction. the re gister content will be updated when a new transaction starts. in error cases the user can track back, which transaction failed. table 494. d2di status register 1 (d2dstat1) offset 0x3 access: user read 76543210 r d2dif d2dbsy 0 00000 w reset00000000 table 495. d2dstat1 register field descriptions field description 7 d2dif d2d interrupt flag ? this read-only flag reflects the status of the d2di nt pin. the d2d interrupt flag can only be cleared by a target specific interrupt acknowledge sequence. 0 external interrupt is negated 1 external interrupt is asserted 6 d2dbsy d2d initiator busy ? this read-only status bit indica tes that a d2d transaction is ongoing. 0 d2d initiator idle. 1 d2d initiator transaction ongoing. 5:0 reserved, should be masked to ensure compatibil ity with future versions of this interface. table 496. d2di address buffer register (d2dadr) offset 0x4/0x5 access: user read 1514131211109876543210 r rwb sz8 0 nblk 0 0 0 0 adr[7:0] w reset 0000000000000000 table 497. d2di address buffe r register bit descriptions field description 15 rwb transaction read-write direction ? this read-only bit reflects the direction of the transaction 0 write transaction 1 read transaction 14 sz8 transaction size ? this read-only bit reflects the data size of the transaction 0 16-bit transaction. 1 8-bit transaction. 13 reserved, should be masked to ensure compatibil ity with future versions of this interface. 12 nblk transaction mode ? this read-only bit reflects the mode of the transaction 0 blocking transaction. 1 non-blocking transaction. 11:8 reserved, should be masked to ensure compatibil ity with future versions of this interface. 7:0 adr[7:0] transaction address ? those read-only bits contai n the address of the transaction
mm912_634 advance information, rev. 4.0 freescale semiconductor 334 4.41.3.8 d2di data buffer register (d2ddata) this read-only register contains information about the ongoing d2d interface transaction. fo r a write transaction the data becomes valid at the begin of the transaction. for a read trans action the data will be updated during the transaction and is finalized when the transaction is acknowledged by the target. in error cases the user can track back what has happened. both d2ddata and d2dadr can be read with byte accesses. 4.41.4 functional description 4.41.4.1 init ialization out of reset the interface is disabled. t he interface must be initialized by setti ng the interface clock speed, the time-out va lue, the transfer width and finally enabling the interface. this should be done using a 16- bit write or if using 8-bit write d2dctl1 must be written before d2d2ctl0.d2den=1 is written. once it is enabled in normal modes, only a reset can disable it again (write-once feature). 4.41.4.2 transactions a transaction on the d2d interface is triggered by writing to either the 256 byte address window or reading from the address window (see staa/ldaa 0/1 in the next figure). depending on wh ich address window is used a blocking or a non-blocking transaction is performed. the address for the transaction is the 8-bit wide window relative address. the data width of the cpu read or write instructions dete rmines if 8-bit or 16-bit wide data are transfe rred. there is always only one transaction active . figure 119 shows the various types of transactions explained in more detail below. for all 16-bit read/write accesses of the cpu the a ddresses are assigned according the big-endian model: word [15:8]: addr word[7:0]: addr+1 addr: byte-address (8 bit wide) inside the blocking or non-blo cking window, as provided by the cpu and transferred to the d2d target word: cpu data, to be transferred fr om/to the d2d target the app lication must care for the stretched cpu cycles (limited by the timout value, caused by blocking or consecutive acce sses), which could affect time limits, including cop (computer operates properly) supervision. the stretched cpu cycles cause the ?cpu halted? phases (see figure 119 ). table 498. d2di data buffer register (d2ddata) offset 0x6/0x7 access: user read 1514131211109876543210 r data15:0 w reset 0000000000000000 table 499. d2di data buffer register bit descriptions field description 15:0 data transaction data ? those read-only bits contain the data of the transaction
mm912_634 advance information, rev. 4.0 freescale semiconductor 335 figure 119. blocking and non-blocking transfers. 4.41.4.2.1 blocking writes when writing to the address window associated with blocking transact ions, the cpu is held until the transaction is completed, before completing the instruction. figure 119 shows the behavior of the cpu for a bl ocking write transaction shown in the following example. staa blk_window+offs0 ; write0 8- bit as a blocking transaction ldaa #byte1 staa blk_window+offs1 ; write1 is executed after write0 transaction is completed nop blocking writes should be used when clearing interrupt flags loca ted in the target or other writ es which require that the opera tion at the target is completed before proc eeding with the cpu instruction stream. 4.41.4.3 non-blocking writes when writing to the address window associated with non-blocking transactions, the cpu can continue before the transaction is completed. however if there was a transaction ongoing when doing the 2nd write the cpu is held until the first one is completed , before executing the 2nd one. figure 119 shows the behavior of the cpu for a blocki ng write transaction shown in the following example. staa nonblk_window+ offs0; write 8-bit as a non blocking transaction ldaa #byte1 ; load next byte staa nonblk_window+of fs1; executed right after the first nop as the figure illustrates non-blocking writes have a performance advantage, but care must be taken that the following instructi ons are not affected by the change in the target caused by the previous transaction. 4.41.4.4 blocking read when reading from the address window associated with blocking transact ions, the cpu is held until the data is returned from the target, before completing the instruction. figure 119 shows the behavior of the cpu for a blocking read transaction shown in the following example. ldaa blk_window+offs0 ; read 8-bit as a blocking transaction staa mem ; store result to local memory ldaa blk_window+offs1 ; read 8-bit as a blocking transaction staa 0 ldaa # staa 1 write transaction 0 write transaction 1 staa 0 ldaa # staa 1 write transaction 0 write transaction 1 nop nop cpu halted cpu halted cpu halted blocking write non-blocking write ldaa 0 ldaa 1 transaction 0 transaction 1 cpu halted cpu halted nop blocking read staa mem cpu activity cpu activity cpu activity d2d activity d2d activity d2d activity
mm912_634 advance information, rev. 4.0 freescale semiconductor 336 4.41.4.5 non-blocking read read access to the non-blocking window is reserved for futu re use. when reading from t he address window associated with non-blocking writes, the read returns an all 0s data byte or word. this behavior can change in future revisions. 4.41.4.6 transfer width 8-bit wide writes or reads are translated into 8-bit wide interf ace transactions. 16-bit wide, al igned writes or reads are tran slated into a16-bit wide interface transactions. 16 -bit wide, misaligned writes or reads are split up into two consecutive 8-bit trans actions with the transaction on the odd address first followed by the tr ansaction on the next higher even address. due to the much more complex error handling (by the mcu), misaligned 16-bit transfers should be avoided. 4.41.4.7 error conditions and handling faults since the s12 cpu (as well as the s08) do not provide a method to abort a transf er once started, the d2di asserts an d2derrint. the errif flag is set in the d2dstat0 register. de pending on the error condition further error flags will be set as described below. the content of the address and data buffers ar e frozen and all transactions will be replaced by an idle command, until the error flag is cleared. if an error is detected during the read transac tion of a read-modify-write instructio n or a non-blocking write transaction was followed by another write or read trans action, the second transaction is cancelled. the cncl f is set in the d2dstat0 register to indicate that a transact ion has been cancelled. the d2derrint handler can read the address and data buffer register to assess the error situation. any fu rther transaction will be replaced by idle until the errif is cle ared. 4.41.4.7.1 missing acknowledge if the target detects a wrong command it will not send back an ackn owledge. the same situation occurs if the acknowledge is corrupted. the d2di detects this missing acknowledge after t he timeout period configured in the timout parameter of the d2dctl1 register. in case of a timeout the errif and the timef flags in the d2ds tat0 register will be set. 4.41.4.7.2 parity error in the final acknowledge cycle of a transaction the target sends two parity bits. if this parity does not match the parity calc ulated by the initiator, the errif and the parf flags in the d2dstat0 register will be set. the par[1:0] bits contain the parity value received by the d2di. 4.41.4.7.3 error signal during the acknowledge cycle the target can signal a target specif ic error condition. if the d2di finds the error signal assert ed during a transaction, the errif and the terrf flags in the d2dstat0 register will be set. 4.41.4.8 low power mode options 4.41.4.8.1 d2di in run mode in run mode with the d2d interface enable (d2den) bit in the d2d c ontrol register 0 clear, the d2di system is in a low-power, disabled state. d2d registers remain accessible, but clocks to the core of this module are disabled. on d2d lines the gpio function is activated. 4.41.4.8.2 d2di in stop mode if the cpu enters the stop mode, any pending transmission is completed. when the d2dclk output is driven low, clock generation is stopped. all internal clocks to the d2dclk are stopped as well, and the module enters a power saving state. 4.41.4.8.3 reset in case of reset any transaction is immediat ely stopped and the d2di module is disabled. 4.41.4.8.4 interrupts the d2di only originates interrupt requests, when d2di is enabl ed (d2die bit in d2dctl0 set). there are two different interrupt requests from the d2d module. the interrupt vector offset and interrupt priority are chip dependent.
mm912_634 advance information, rev. 4.0 freescale semiconductor 337 4.41.4.8.4.1 d2d external interrupt this is a level sensitive active high external interrupt driven by the d2dint input. this interrupt is enabled if the d2die bit in the d2dctl1 register is set. the interrupt must be cleared using an target specific clea ring sequence. the status of the d2d input pin can be observed by reading the d2dif bit in the d2dstat1 register. the d2dinit signal is asserted also in the st op mode; it can be used to leave these modes. figure 120. d2d exte rnal interrupt scheme 4.41.4.8.4.2 d2d error interrupt those d2d interface specific interrupts ar e level sensitive and are all cleared by wr iting a 1 to the errif flag in the d2dstat 0 register. this interrupt is not locally maskable and should be tied to the highest possible interrupt level in the system, on a n s12 architecture to the xirq. see the chapter ?v ectors? of the mcu description for details. figure 121. d2d internal interrupts 4.41.5 initializat ion information during initialization the transfer width, clock divider and timeou t value must be set according to the capabilities of the targ et device before starting any transaction. see the d2d target specification for details. 4.41.6 application information 4.41.6.1 entering low power mode the d2di module is typically used on a microcontroller alon g with an analog companion device containing the d2d target interface and supplying the power. interface specification does not provide special wires for signalling low power modes to the target device. the cpu should determine when it is time to en ter one of the above power modes.the basic flow is as follows: 1. cpu determines there is no more work pending. 2. cpu writes a byte to a register on the analog die using blocking write configuring which mode to enter. 3. analog die acknowledges that write sending back an acknowledge symbol on the interface. 4. cpu executes stop command. 5. analog die can enter low power mode - (s12 needs some more cycles to stack data!) ; example shows s12 code sei ; disable interrupts during test ; check is there is work pending? ; if yes, branch off and re-enable interrupt ; else ldaa #stop_entry staa mode_reg ; store to the analog die mode reg (use blocking write here) d2die d2dint d2dinti to read data bus (d2dstat1.d2dif) ackerf cnclf timef terrf parf errif d2den d2derrint 1
mm912_634 advance information, rev. 4.0 freescale semiconductor 338 cli ; re-enable right befo re the stop instruction stop ; stack and turn off all clocks inc. interface clock for wake-up from stop the basic flow is as follows: 1. analog die detects a wake-up condition, e.g. on a switch input or start bit of a lin message. 2. analog die exits voltage regulator low power mode. 3. analog die asserts the interrupt signal d2dint. 4. cpu starts clock generation. 5. cpu enters interrupt handler routine. 6. cpu services interrupt and acknowle dges the source on the analog die. note entering stop mode mode with d2dswai asserted the clock will complete the high duty cycle portion and settle at low level.
packaging mm912_634 advance information, rev. 4.0 freescale semiconductor 339 5 packaging 5.1 package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ae suffix 48-pin lqfp48 revision 0
packaging mm912_634 advance information, rev. 4.0 freescale semiconductor 340 ae suffix 48-pin lqfp48 revision 0
packaging mm912_634 advance information, rev. 4.0 freescale semiconductor 341 ae suffix 48-pin lqfp48 revision 0
packaging mm912_634 advance information, rev. 4.0 freescale semiconductor 342 ap suffix 48-pin 98ash00962a revision g
packaging mm912_634 advance information, rev. 4.0 freescale semiconductor 343 ap suffix 48-pin 98ash00962a revision g
revision history mm912_634 advance information, rev. 4.0 freescale semiconductor 344 6 revision history . revision date description 1.0 11/2010 ? initial release. preliminary. 2.0 4/2011 ? advance information release. 3.0 5/2011 ? added a note to the ordering information table defining the addition of r2 to the part number ? updated the table 3 part numbering scheme 4.0 5/2011 ? corrected errors in table 49. esd and latch-up protection characteristics
document number: mm912_634 rev. 4.0 5/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners ? freescale semiconductor, inc. 2010-2011. all rights reserved.

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